Hey Chip
rjo__
Posts: 2,114
in Propeller 2
Tubular thinks I need more P2's. He's probably right. I am erecting a tower, with 3 P123's and a couple of those other A9's in it,
but I am afraid I am going to knock out the local power station with it. And then I got to thinking... "why should I have all the fun?"
and more importantly: "what will I do when I run into a trivial problem that I can't explain to anyone else?"
Next time you fail to eat enough fiber and are just sitting there waiting,
how about a multi-P2v release for the A9 sect?
but I am afraid I am going to knock out the local power station with it. And then I got to thinking... "why should I have all the fun?"
and more importantly: "what will I do when I run into a trivial problem that I can't explain to anyone else?"
Next time you fail to eat enough fiber and are just sitting there waiting,
how about a multi-P2v release for the A9 sect?
Comments
Not sure what you are asking ? - the A9 build is already less than a single full P2, with 16 COGS, more RAM, but just 18 Smart pins.
That may even have nudged down a little too, as Chip has gone rather quiet - likely he is either deep in testing the PAD Chips, or trying to get an A9 fit...
We have a family of P2's. On the top is the full P2v with an A9. Within the family we have P2v's with less RAM, fewer smart pins etc.
What I am suggesting is to create a platform to study the parallelization of the final silicon... by using multiples of one of the smaller P2v's on the A9 platform. Two should be enough. Ideally, they wouldn't be connected in Verilog, simulating the real world case of independent chips. I could be wrong about this part: The only thing that would be "fake" would be that the second P2v would have to be set-up so that it could be loaded through the first P2v using serial.
In one of the threads a while back I asked if two chips using phased clocks could be used to improve signal bandwidth performance... the answer I got back was "yes." So, I think there is an engineering reason to do this...
But my real motivation is that I think it is always going to be faster for two P2's to talk to each than it will be to get a P2 to talk to almost anything else. So, I'd like to get them talking now. My solution is to start stacking the FPGA boards, but it isn't exactly elegant, and I am going to end up talking to myself:)
If you want to test P2-P2 links, those will always be via-pins, so having them both in one FPGA is not going to help, and has risks in that it is harder to separate and phase the clocks.
Sounds like this testing is best done with at least 2 FPGA boards, as you can then check both any-phase, and sync'd clock cases.
Thanks