SPI flash dilemma
cgracey
Posts: 14,210
I've been looking over data sheets for the biggest of the 3-byte-address 8-pin SPI flash chips:
Winbond W25Q128FV (most available and cheapest)
Micron N25Q128A
Cypress S25FL127S
ISSI IS25LP128
These are all 16Mx8 chips which are backward-compatible with smaller-memory devices.
I'm trying to determine what is required to effectively reset these SPI chips on a Prop2 reset, where the SPI chip may still be in another mode from before the reset. This is difficult and seems indeterminate, at this point.
I thought of one thing that would mitigate this problem and save an I/O pin: committing to single-wire I/O, while connecting DI and DO to the same Prop2 I/O pin. This would limit read speed to ~1/4th of quad SPI, but data could still be read at 10MB/s at 160MHz clock speed, making the load time for 512KB only 50ms. Switching directions on the data pin is trivial. Doing this would close the door on quad SPI, but we'd at least never have to worry about the SPI flash being in a dual- or quad-mode when the Prop2 resets. It would also free an I/O pin.
How do you feel about this?
Winbond W25Q128FV (most available and cheapest)
Micron N25Q128A
Cypress S25FL127S
ISSI IS25LP128
These are all 16Mx8 chips which are backward-compatible with smaller-memory devices.
I'm trying to determine what is required to effectively reset these SPI chips on a Prop2 reset, where the SPI chip may still be in another mode from before the reset. This is difficult and seems indeterminate, at this point.
I thought of one thing that would mitigate this problem and save an I/O pin: committing to single-wire I/O, while connecting DI and DO to the same Prop2 I/O pin. This would limit read speed to ~1/4th of quad SPI, but data could still be read at 10MB/s at 160MHz clock speed, making the load time for 512KB only 50ms. Switching directions on the data pin is trivial. Doing this would close the door on quad SPI, but we'd at least never have to worry about the SPI flash being in a dual- or quad-mode when the Prop2 resets. It would also free an I/O pin.
How do you feel about this?
Comments
By limiting to single-wire, we narrow the unknowns way down at the expense of read speed. Write speed will always be dominated by program/erase times. It seems to me that the cost of allowing quad SPI (3 more pins, plus reset difficulties) is quite high, given the probable read-seldom use of the SPI flash.
My pick was the W25Q128FV mainly because I've had some experience with Winbond .
SPI_SEL = 61
SPI_CLK = 60
SPI_DI and SPI_DO = 59
Here is what it would look like to support quad SPI:
SPI_SEL = 61
SPI_CLK = 60
SPI_DI = 59
SPI_DO = 58
Here is what it would look like to implement quad SPI:
SPI_SEL = 61
SPI_CLK = 60
SPI_D3 = 59
SPI_D2 = 58
SPI_D1 = 57
SPI_D0 = 56
The $9F command reads ID across all four devices.
This could really help with programming.
That'd be kind of ugly, as it relies on the authentication signature, but it'd only affect timing if you were in stuck in QSPI, othertimes it'd just boot deterministically.
Ugh - That seems rather a retrograde step, as QuadSPI parts are now the cheapest and it is not a good look to say to someone who has a Quad part on their board "Oh, we decided to block using Quad mode.."
Anyone who does want/need QuadSPI, now has to mount TWO flash parts on the board, consuming more pins, and their boss will ask "Why do you have two flash parts ?!"
Programming & admin gets a lot more complex, as now you have two flash images to manage...
Or, just apply the exit commands first, as was suggested in another thread.
Peter has already tried this, on some parts, and found parts tolerate the 'not my reset' commands, as expected.
I can think of multiple Font and Image uses, where the 'seldom' is untrue.
Then, there are XIP applications, where read is part of the code-pathway, and here speed certainly matters.
There is a Boot-map already, for skipping UART poll for example, can that extend to allow a user choice of flash-config ?
3 pin mode has merit for smaller applications, but not at the expense of higher performance ones.
I would also include the cheapest flash parts on any device list too.
Right now, that seems to be ~ 25H16 (2M x 8) from Fremont. ~15c
That part does document a Quad mode exit.
The parts I looked at gave reset info, some mentioned 0xff, 0xffff, and some (larger/newer), a new byte pair.
If a part fails to define mode-exit, you have a couple of choices :
a) Move it onto a '1-bit mode only 'list, here, provided the user never flips into Quad, they have little risk
b) Test the part, if the price is compelling enough, and add it to a 'Verified Quad Exit' List.
Vendors who cannot be bothered to define mode exit cases, deserve to move down everyone's BOM list.
Only the QPI mode remains active after a CS high. This can be reset to SPI on most Flash chips with the command $FF sent in QPI mode (ISSI says $F5).
Alternatively you can send the Reset sequence $66,$99 in QPI mode as first boot activity. This will not be valid commands in SPI mode, because CS goes high after 2 bits:
The Flash Pins IO2 and IO3 must have Pullups so that Hold and WE is high in SPI mode. It should be possible to use these pins also for Boot mode select (Skip Flash boot), and maybe as SDcard Chipselect.
Andy
Smaller parts seem to lack the 'sticky quad' mode, and so always accept commands on D0 only.
Larger parts I looked at, added a 'Keep Sticky quad' bit in the dummy bytes area of the address, on D0.
That means those parts can also exit quad, using only D0
Of course, commands aside, that still leaves the question of handling WP#/IO2, HOLD#/IO3.
If the ROM does not define those, users will need to add external pullups.
Is there not enough spare mapping in the Boot-pin checks, to include both a 3 Pin SPI and a Quad SPI choice ?
3 Pin has smallest pin-cost, with some caveats/limits & Quad allows one Quad part to do boot(in single mode) and run in Quad for more demanding applications.
There are some applications that will either have to calculate large tables or remember them and then access them as fast as
possible. For those kinds of apps, gaining access to that data is effectively part of the boot process, since booting the hardware isn't really
done until it can actually start working.
I've been looking at more data sheets, like a 17-cent 4Mb flash. It has different commands than the others. One sure thing is read ($03), in 1-bit mode, across all devices.
My big problem now is that I want to finish the ROM, and I'm not enthused about large code that tries every possibility for flash boot. I need something simple and reliable that can be known-good.
It seems futile to chase down dozens of specs to suss out the most common procedures for escaping dual/quad modes and cancelling operations in progress. I need simple.
I'm really thinking the 3-pin solution is best. It keeps people from entering dual/quad modes, in the first place. And I would rather not be twiddling three more pins on boot-up, especially on lower-pin-count Prop2's.
Sorry to be a stick-in-the-mud. I might change my mind, but at this point I only feel sanity with a 3-pin solution.
thanks
AT25SF041
Digikey
Chip,
1) the Winbond and ISSI parts have the max current draw 25mA or below. This parts can be power supplied directly from the prop pin.
For other (all) parts, the prop reset line can drive a transistor with a series diode to supply power to them from 5Vcc (to 3.1V) which many boards will have available on-board.
Thus reset can be done by cycling power.
2)Winbond and Cypress have a separate RESET pin in their 16 pin packages. This can be directly connected to the prop reset.
I believe that during the POR and also the sw (warm) reset the prop drives its external reset pin low to allow for reset of other external components.
3) Except for the ISSI part, which do not have a hw reset function/pin, all the other parts have a functional reset (on shared pin) when deselected.
So I will definitively at least support the QuadSPI. You can do this way:
- assumption: if separate pin is available (16 pin parts) it will be connected to prop reset pin. This will warranty reset in any circumstance.
1) with CS high issue a 1us pulse on IO3/RESET (this will reset the parts that have shared pin for reset)
2) then issue FFh(ExitQPI)/66h(EnableRST)/99h(RST) command sequence at max 20MHz (this will reset once more in the case point 1 is not supported)
3) start interacting with the flash.
This should work under a lot of conditions and provide the user with many parts to chose from his flash chip.
BTW if for "implement" you mean by software (in the ROM), to "support" (eventually allow user to implement it later) you still need the full pin-out from the beginning so that you can use the shared pin RESET function and that the data IO lines are ordered and aligned (thus not requiring additional pasm instructions to adapt the packet)
At 25ma from a port pin the voltage drop would be too great but even if they are designed to work at lower voltages you still have the problem that the interface is running at 3.3V when its vdd may be down to 2V. Then the part ends up with noise on its vdd especially from the clock bleeding through the esd diode.
If "the boss" is asking me why I have two SPI Flash chips I will tell him "what was I thinking" but perhaps he would like to design it instead without the 15 cent Flash. I am quite happy to have a another chip if I ever need it but I'd rather keep the boot sequence straightforward and the dedicated pins to a minimum to allow for flexibility in design.
The winbond part on the table QPI commands) on the page 27 gives 2 clocks for the exit code FFh. I understand from this that to exit the Quad mode you need to transmit the command on all 4 the IO lines. But I do not see any issue on this since it support both the dedicated and shared RESET pin function. Thus the exit can be done through the hw command.
Anyway, it is still possible to cycle power through a transistor driven by the prop reset pin. And this only in case a flash without a reset pin is chosen and used in QPI mode. This is up to the user who can chose a different part if he wants to use QPI.
Considering how many devices can share the SPI bus, even if quad, having 6 pins, of which all except CS can all be shared among other SPI devices, it's not a waste in my opinion. This allows for hw reset of the flash, independent from modes and sw commands, and still allows many parts to chose from.
Edit:
And the request of a flash that have a dedicated or shared reset pin to allow the use of QPI is acceptable for me.
And whats is disheartening is that sometimes I really do not understand some people here:
- the SD boot: NO! You have to use a flash to boot and then read whatever you want from SD if you need it !
- the QPI mode: NO! You have to use a SPI flash to boot and then if you need a second flash to be used in QPI
Don't be too disheartened, we are only sharing opinions, and although we are not trying to spar, it sometimes seems that way
I don't understand why we can't just boot in SPI mode and then have the option of accessing the same chip in QSPI. Yes, there is a problem with SPI Flash in general, they certainly are NOT standardized, even if the commands were, the configurations are not. But that is where SD is absolutely stock standard and also why we should have it in a system as that is the only serial memory that the boot loader really knows how to program.
Edit:
I think the concern is that some multi-bit SPI flash modes (for some chips) must be explicitly disabled to get back to the more-standard 1b mode. I think Chips concern is having to accommodate this during resets. My thought is: don't. Let the board designer who wants to use one of these chips with sticky multi-bit modes be responsible. The P2 expects "standard" 1b mode on boot, and it is up to the designer to ensure their chosen flash chip is in that mode.
But the booter must be able to load their program, first.
Okay. Maybe I'm misunderstanding the problem (see edit of my prior post). If the booter requires an SPI flash that's in a "standard" 1b mode on boot (using the 4-pin layout), what more is required?
With the 4-pin layout, some customers will connect up the other 3 data pins and configure the device for QPI. If a warm reset occurs, it becomes very difficult to get back into 1 bit mode, as there is no standard.
The point is that it might be desirable to use the flash in QSPI mode when it's used for file storage.
This is what I think also, but using after the boot the chip in QSPI implies that in case of warm reset (perhaps external watchdog circuit) the ROM boot code will be able to boot ie revert back to standard SPI.
Now the simplest way to accomplish this is to use chips that have dedicated/shared RESET pin.
Dedicated RESET pin (on 16pin parts) can be connected to the prop reset pin, provided that during the sw reset the external pin is driven low. This is transparent from the prop perspective
Shared pin is part of the QSPI interface and can be driven low (by bootcode) with CS not asserted (high). This is sw driven by prop.
Both the solutions will certainly bring back to SPI any flash chip supporting hw reset. This don't mean the boot will happen in QSPI, but IO3 to reset the flash must be driven by prop during boot. Thus this require that all the QSPI signals are reserved on certain pins. It requires the signals that Chip calls "implemented", "supported" is not enough.
But again, having pins 56..63 dedicated to (q)spi/serial on a total of 64 IO is not a waste for me, specially if you consider that 5 on 6 pins for (q)spi can be shared among multiple devices. That only means that SPI devices/drivers will always use the higher numbered IOs rader than 1..4 for example.
Edit:
... and to clarify: that not means that users must chose flash with reset, but that the ROM boot code will issue a 1us pulse on IO3 (prop IO-P59) prior to start booting. If the user do not intend to switch to QSPI he can use a flash without hw reset pin. The normal non QSPI flash chips will simply be wired on pins 56,57,60,61
The chip will stay in 4b mode even after the power is cycled to the chip? Yeah, I guess that would be difficult to externally reset. Maybe you just say that those particular chips/modes are not compatible with the boot ROM, and leave it at that. If someone really needs this, they will end up with two flash chips. Fortunately, this will only use up 7 pins (since CLK and 2 DATA lines can be shared), which is only one more (the 1b SPI's CS line) than if just using the QSPI chip by itself.
No, both "power cycle" and "hw reset" will revert back the flash chip to 1b mode. But this is not true for prop warm/sw reset. Using 16 pin flash which have external reset it could be transparent to the prop IF the sw reset drives the external reset pin low. If not or in case of 8 pin flash the prop must issue an reset to the flash chip, the easyest way is using the shared IO3/RESET pin when CS is high.
The shared reset pin works always as reset in 1b mode while it works as IO3 with CS low and RESET with CS high in 4b mode. This for all the flash chips having reset pin that I've seen.
@cgracey: the p2 is driving its reset pin low during sw reset isn't it?