Simple Computer based on gates

Cluso99

I have been interested in building a simple computer using just gates. I have seen the SAP-1 and variations.

I know I could just use an FPGA and be done with it, but that is not what I am after.

Currently I have an smt 2 layer pcb layout 4"x4" that has 16 rows x 10 columns of single gate chips, with small pads for interconnecting using thin (kynar) wire. The gates used are 6-pin centre powered (pins 2 &5) SOT23-6/DBV (0.95mm pitch) although I have been thinking of using SOT363/DCK (0.65 pitch).

The following gate chips (6pin)are interchangeable on the pcb...
74LVC1G10 3 input NAND
74LVC1G27 3 input NOR
74LVC1G386 3 input XOR
74LVC1G373 Transparent TriState D Latch
74LVC1G58 2 input NAND/OR/XOR/INV configurable
74LVC1G98 2 input NAND/NOR/INV/MUX configurable
Of course there are other pin compatible chips too, but these form the basic gates required.

I have also thought about using some bigger gate chips
74LVC1G99 2 input NAND/NOR/INV/AND/OR/MUX + T/S output configurable (8pin)
and/or
74AUP2G58 Dual 2 input NAND/OR/XOR/INV configurable
74AUP2G98 Dual 2 input NAND/NOR/INV/MUX configurable

Initially I would use one pcb to do the Accumulator, B Register, ALU (8 bit), and interface to the 8bit bus.

I would exercise the board using a propeller chip of course!!!

KeithE

You could potentially figure out a flow where you could:

-draw schematics for your design
-generate a verilog or vhdl netlist
-simulate your design in verilog or vhdl (potentially target an FPGA)
-finally build your design with your ICs

Then before you build you know that you haven't made any fundamental design errors, and if anything goes wrong you can compare the actual results with the expected. If you download the Altera software it includes a version of Modelsim which should handle a design of this complexity. (See software used for the low-end Terasic boards such as the DE-Nano-SoC which has a dual core Cortex-A9 that runs linux.)

jmg

Cluso99 wrote: »

I have been interested in building a simple computer using just gates. I have seen the SAP-1 and variations.

I have to ask, Why ?

There was a Micro-coded 8051 in the news, that claimed ~300 LEs

KeithE wrote: »

You could potentially figure out a flow where you could:

-draw schematics for your design
-generate a verilog or vhdl netlist
-simulate your design in verilog or vhdl (potentially target an FPGA)
-finally build your design with your ICs

You missed the steps of
- Generate a routing plan for the Sea-Of-Gates
- Import the Net+Auto-Routes into a CAD pgm like KiCad, with pre-placed Gate&CAP arrays.

Rather than a Sea-Of-Gates approach, which seems a dead-end to me, I think it makes more sense to find a
"Smallest FPGA/CPLD " that can run a useful Micro Core.

Working backwards from package, & excluding BGA, the candidates currently look to be QFN32 or QFN48 ?

Here, the challenge is less the core (there are a ton of those already) and more around the Memory interface.
With QuadSPI being the cheapest/smallest memory, that seems the logical memory choice.
Perhaps 1 x QuadSPI SRAM and 1 x QuadSPI Flash ?

rosco_pc

jmg wrote: »

Rather than a Sea-Of-Gates approach, which seems a dead-end to me, I think it makes more sense to find a
"Smallest FPGA/CPLD " that can run a useful Micro Core.

Or you can do both: http://blog.notdot.net/2012/10/Build-your-own-FPGA



anyway very cool what you're doing Cluso99 and looking forward to the end result.

Heater.

Why?

Because. Because people who are interested in electronics and logic and computing tend to find themselves becoming fascinated by the challenge. The challenge to write ones own assembler, design ones own language, write a compiler build a computer from scratch, make ones own transistors http://hackaday.com/2010/05/13/transistor-fabrication-so-simple-a-child-can-do-it/

It's crazy and pointless but many hobbies are. It's no more crazy and pointless than spending hundreds of hours playing video games, solving crossword puzzles or a million other crazy and pointless things people do.

I have found myself making a 4 bit binary counter out master-slave flip flops built from dozens of BC108 transistors and LEDs on a prototyping board. I just happened to have a bag of a thousand or so BC108s lying around, what else am I going to do? Not to mention writing and emulation of the Z80 microprocessor for the Propeller.

The home made CPU idea crosses my mind occasionally. The challenge of course is how simple you can make it such that it does actually run programs of some kind but is a small enough design to actually complete the thing. I would be tempted to not go as low level as individual NAND gates and such but allow myself the luxury of flip-flops, shift registers, ROMs and such. The kind of thing that was all the rage in TTL chips back in the 1970's.

To that end I was always drawn to the single instruction computer idea. http://esolangs.org/wiki/OISC. If you only have one instruction you don't need an instruction decoder. If that instruction is something like "SUBtract and branch if Less-than or EQual to zero" (SUBLEQ) then you can write any program with it. http://esolangs.org/wiki/subleq.

The neat thing about the subleq is that there is a compiler for a C like language available for it.

Cluso99

I am not interested in using an FPGA for this.

I hand routed a Xilinx FPGA in the early 1990's for interfacing to the backplane of the ICL System
25. I built a 16 Serial Port board to plug into the bus for some ICL customers.
It was a very interesting exercise and paid handsomely too
The FPGA provided a means to change the bus interface if I got something wrong with the poor documentation available - we were not supposed to attach things to the bus!

I have programmed in 80486 Assembler an emulation of the ICL System 25 computer, and had it verified.

This is just something different. Build the ALU from gates, not an ALU chip like the 74xx181 or 74xx283. After ADD & SUB, I can extend to doing some other things.

Basically I want to build a pcb that has a "sea of gates". Then I can route the pcb using wire, so I can update and/or fix anything if necessary. I am going to use smt and my oven to solder the pcb.

Currently thinking whether to build the pcb with just the same gates, or put some different gates in various columns.

The ALU plus A & B Registers, with the Instruction Register and Decoder should fit on the one pcb. Might also see if I can get the PC on the pcb too.

As for RAM/ROM, I will initially use a prop to emulate this and the Memory Address Register. Later I will use an SRAM (8Kx8 or larger) and an address latch. Probably an Input and Output register with Switches and LEDs on a board.

The pcb connections between the gates will be on 0.050" pitch.
The external 8-bit bus will be on 0.1" pitch.

Tor

Great idea. Much more fun (although much more work) than FPGA.
There have been several projects for re-making a 6502 CPU in TTL logic, the latest one I'm aware of is cycle-perfect even for (NMOS 6502) undocumented opcodes, and should run at 20MHz(!).

Leon

The early Cray computers were mostly built from ECL gates.

Cluso99

Leon wrote: »

The early Cray computers were mostly built from ECL gates.

The Friden/Singer/ICL System 10 (1969-1980) was built from 7400 TTL logic and core memory.

kwinn

How about building a single bit alu and shifting the data through it to execute instructions. That would simplify the circuitry and let you try out instructions and data with variable bit lengths.

Cluso99

An 8 bit ALU is not that complex, especially if you don't use look ahead carry. It also depends on other functions besides add and subtract, such as AND, OR, XOR and things like SHR, ASR, ROR, RCR and their Left equivalents, INC, DEC, NEG, etc. Then comes CMP, and the Flags.

The one thing in the SAP-1 that seems restrictive to me is the 4bit PC and therefore 16 bytes of RAM. So I will probably make my PC and MAR 8 bits wide for future expansion.

I have been thinking about the use of a B Register. Current thoughts are that a B Register may not be necessary as the RAM data (ADD/SUB) could be forwarded directly to the ALU provided the ACC can latch the result directly instead of via the bus. Also I need to check the ACC register (register implementation) can latch the result without upsetting its output to the ALU.

localroger

The HP2100A (first computer I had access to at the age of 10 in 1974) had only add, not, and, or, xor, and shift/rotate. To subtract you would NOT, add 1, then add.

kwinn

You may or may not get by without the B register. The adder/subtractor needs have stable A and B inputs to produce a valid and stable output, and that output then has to be written back to the accumulator or memory via the bus. Depends on the accumulator design, but judging by the block diagram I would guess the B register is needed.

kwinn

8Kx8 ram is a good idea, and an 8Kx8 eeprom or eprom along with a counter and a couple of decoder chips could be used to replace the propeller as the controller/sequencer at some point. Looks like you will need at least 20 outputs from the sequencer.

guenthert

You got already the inspiration. There might be times when the goal seems unattainable, then look at
http://members.iinet.net.au/~daveb/simplex/ringhome.html

My favorite is the magic-1: http://www.magic-1.org/

but also the Forth computer Mk1 has its charm and might be a more realistic goal: http://www.aholme.co.uk/Mk1/Architecture.htm

Buck Rogers

guenthert wrote: »

You got already the inspiration. There might be times when the goal seems unattainable, then look at
http://members.iinet.net.au/~daveb/simplex/ringhome.html

My favorite is the magic-1: http://www.magic-1.org/

but also the Forth computer Mk1 has its charm and might be a more realistic goal: http://www.aholme.co.uk/Mk1/Architecture.htm

Strange, I know the chap behind Magic, as do most of us who run OpenWRT firmware as the idea was started by his brother.

Cluso99

Thanks for the links. The Magic 1 was quite an undertaking.

I've been drawing in my head the logic necessary and have realised that the SAP-1 can be simplified further . So that is the way I am going to proceed... See how small I can make it

Cluso99

while working on the schematic I have placed this into the blocks. There is no need for a few sections I the SAP-1.

Now I am thinking that each block can be done by a prop, stacking them up. Later, one by one, the blocks can be replaced by the real block. In the process, a simpler micro can be made more complex too.
I will post a bit more in a few days about what I am thinking now

jmg

Cluso99 wrote: »

Now I am thinking that each block can be done by a prop, stacking them up. Later, one by one, the blocks can be replaced by the real block.

I see you are now using the Prop as a PLD, so why not use a real PLD ? - things will work faster ...

Possible candidates, with some RAM and PLL, could be
Lattice ICE5LP1K-SG48 / ICE5LP2K-SG48 / ICE5LP4K-SG48
All those are less than a Prop in price.

The Altera MAX10 10M02 comes in at less than P1, and 10M04 is roughly the same.

Simplest to use package in MAX10 is 144-EQFP (20x20), but I notice they offer 10M02 only down to 3x3mm BGA36
If they can fit a 10M02 into a 3x3 BGA, it's a pity they don't offer a QFN48 ?


Altera 10M02 : 2000 LE 110592b RAM 27 io $2.84/1k in BGA36 (vs $5.54 for 144-EQFP)

Lattice have 2 similar parts in ICE40 Ultra series in small packages

Lattice: 2048 LE 81920b RAM 26io BGA36 2.5 x 2.5mm $3.74/1k
or
3520 LE 81920b RAM 26 io (BGA36, 2.1x2.1mm) or 39 io (QFN48 7x7mm $5.25/1k )

The larger Lattice part has similar LE/$ to the Altera part.

The SOT23 size of those BGA packages is appealing, but the handling rather less so.
Going down I see ICE40UL1K
1248 LE 57344b RAM with either
10io 16-WLCSP (1.4x1.5) 1.36/1k
or
26 io 36UCBGA (2.5x2.5) $1.82/1k

Altera can do a 10M08 in 81VBGA, (4.5x4.4) at $17.28/1k
Gives 8000LE 387072b RAM and 56io
Strangely, the 10M08SCU169C8G in BGA169(11x11mm), 130io, is much cheaper at $8.37/1k ?!

I see Altera stock both 1.8V 166MHz and 3V 100MHz HyperRAM (6x8mm)

KeithE

As far as I can tell SAP-1 only has LDA, ADD, SUB, OUT, and HLT instructions. So it doesn't seem interesting enough to build. I assume you would look at SAP-2 for inspiration and add some branching instructions too?

When I was in college one of the project I was looking forward too was building a subset of the 68000 with bit-slice logic, but then in my year they changed the project. What a bummer! We had the famous Mick and Brick book as one of the textbooks, but I admit that it didn't inspire me.

Cluso99

Jmg,
As I said earlier, I am not interested in FPGA or cpld.

I have thought that I may use a prop for each block as a simulation. Later, one by one I would replace the prop with 74LVC chips.

I can start with a simpler SAP version. Later, expand it to add more instructions and ALU features too.

I require JMP so I am using 74LVC161 x2 so I can preload for a jump.

I require

KeithE

If you've never read about these, you might find it interesting:

https://en.wikipedia.org/wiki/AMD_Am2900

Check out the list of computers which used them.

Heater.

Hmm, the list of computers using AMD 2900 does not include the GEC-Marconi Locus 16.

The Locus 16 had been built in TTL years before. In 1978 or so they had a 2900 bit slice version.

The Locus was an embedded computer used in 3D radar http://www.radartutorial.eu/19.kartei/02.surv/karte008.en.html and other military projects.

I was scratching my head one day wondering why our new multi-processor, shared memory, software was failing. Eventually I figured out the CPU team had not yet implemented the "lock exchange" instruction in the micro-code of the new 2900 based processor!

KeithE

Heater - it's your chance to attempt an edit.

Heater.

I thought about that.

Problem is I can't find any info on the Locus 16 on the net to reference. Sadly all the documentation on it I had myself has been lost long ago.

It was all "hush hush" military stuff. I'm probably subject to the death penalty for talking about it.

Dave Hein

Sometime in the early 80's I built a 16-bit controller using 4 2901s and a 2904 that controlled program flow. The system controlled a video processor that simulated video compression algorithms. I published a paper on it in one of the IEEE journals. I'll have to see if I can find it online somewhere. After I built it I recall thinking that maybe I could have used a Z80 for the controller instead, but I don't think it would have met the precise timing requirements that we had.

Heater.

I remember spending hours reading data sheets and whatever info I could find on those bit slice chips. Fascinating stuff for a non-cs major like me. Seemed like such a cool idea to do something with them.

It all went obsolete before I could get my head around it !

The Locus 16 was pretty amazing. The Marconi company had been building it's own computers for embedded systems for ages. The originals were built with transistors. Later came TTL chip versions. Then the bit slice thing. It was like the PDP 11 or Data General Nova. But smaller, rugged for military use. And you could hang a bunch of processors off the same memory bus for a bit of a parallel performance boost. They had high level language compilers (Corral 66) an operating system and all kind of tools for it.

Me, I was just a young "green horn" who knew nothing much about building computers and system software, being a physics graduate. Amazed at finding myself in a place where such things were going on. We youngsters were soon meeting our given goals with Motorola 6800/6809, Intel 8051 and whatever.

KeithE

I was interested in the history of the AM2900 family and found this:

http://archive.computerhistory.org/resources/text/Oral_History/AMD_2900/102658341.05.01.pdf

User Name

KeithE wrote: »

Check out the list of computers which used them.

The hardware of the "The Lilith computer designed at ETH Zürich by Niklaus Wirth" was actually part of Richard Ohran's graduate thesis at ETH Zürich. The first production Lilith and I once spent many months in the basement of a bank building somewhere.

Dave Hein

I was going through some boxes I had in storage and came across the paper that I presented at an IEEE Circuits, Systems and Computers conference in 1983. The paper described a video compressor system that used a 2901 controller. The block diagram is shown in the attached image. The controller used 4 2901's to make a 16-bit computer. It had a 4Kx16 data RAM, and a 1Kx64 instruction RAM.

The 64-bit instruction provided lots of lines to control the ALU, sequencer and the video compression unit without having to decode the instruction bits. I recall writing a meta-assembler for it where I could define instructions as macros. I wrote the meta-assembler in Ratfor, which is a C-like language that is converted to Fortran.

Heater.

Wow.

I mean WOW!

As a graduate "green horn" I found myself working with a team that had built a 16 bit processor for military systems using AMD 29'whatever bit slice chips. An upgrade from their 74xx TTL processor.19282 I think. So I spend many an evening studying the data sheets and so on.

By the time I figured out what to do with it, it was obsolete!

This became a pattern for the rest of my career