More Shuttle choices
jmg
Posts: 15,175
in Propeller 2
Just got the below email, claims 100 tested parts in a shuttle for $70k $50k at 65nm..
Could offer more choices for any P3 ?
Could offer more choices for any P3 ?
BaySand introduces the ASIC UltraShuttle-65, a unique Multi Project Wafer which comes to bridge the gap to real ASIC and Silicon access.
At a cost of $70,000 BaySand delivers 100 fully tested ASIC/chips at 65nm process node.
It includes:
RTL signoff support
Layout and timing closure
DFT, ATPG and BIST
Design review and signoff
Delivery of 100 fully tested parts
BaySand is offering a discounted price of $50k for the first 100 users signing before the end of August 2016!
For more information click here!
Best regards,
Joshua G.
Marketing Manager
Joshua@baysand.com
www.baysand.com
Comments
So the special P2 smartpin and ADC/DAC edge layout cannot be done in their method.
Also, the chip size is limited to the number of gates in their standard layout - no mention of the size.
Could be ideal for a P1V though ???
No mention of price either.
I wonder how the Configurable P2, which Chip has recently added, can map onto this resource ?
"The Shuttle is for the FG65L-5 device, which is a 65nm technology up to 600,000 usable gates, up to 900kbit of memory, 4 PLLs/DCMs with maximum of 242 user IOs."
.. and what MHz that could deliver, in 65nm ?
P1V takes most of the DE0-Nano which is a Cyclone IV with ~22K LEs.
P2 currently takes almost all of a Cyclone V A9 with ~301K LEs.
Therefore P2 is approximately 13.7x more complex than a P1 (in terms of LE usage).
It has been estimated that an LE is equivalent to 1-20 gates, so lets say ~8 gates.
P2 then would require 301K x 13.7 = 4,124,000 gates.
P2 also has 512KB Hub + 16* 4KB Cog = 576KB = 4,608Kb.
Doesn't look like the FG65L-5 device is going to go anywhere near cutting it for a P2 !
It seems some kind of standard cell ASIC mixed with PLL, memory, and IO blocks. They do not use the GDS file as a real shuttle will do. Instead they ask the customer for the RTL, so this is perfect for P1v.
Kickstarter numbers: 100 pcs @ $50,000. Half NRE between parallax and backers. This means that parallax pay $25,000, and each backer will get each P1V @65nm for $250/pc.
I bet that 100 pcs will sell in just the first day.
If not sure about such success, I also have plan B: parallax will pay $30,050, and the maximum number of backers will be limited to 50. Each of this 50 fortunate forumistas will pay $399 to get a P1V @65nm.
Ken, are you listening?
How many customers did bought the P2 FPGA? Does this numbers make sense?
Of course, this would use quite a bit of static power as you have a 600K gate design even if you only use half those gates.
No mention of any Flash/OTP.
900kb ram = ~112KB
Presuming all is usable (can be routed in blocks)
8 cogs • 2KB + 96KB hub
8 cogs • 4KB + 80KB hub
16 cogs • 2KB + 80KB hub
16 cogs • 4KB + 48KB hub
Presuming success, how much are future chips going to cost ??? Bet they will be expensive ASICs as they own the lower level ASICs IP.
Perhaps there might be enough prop heads with small quantity requirements to get together to do a 100 pc run at $500/chip.
Because the shuttle is not just a one-off job. According to baysand, they have 'high volume support'. It makes no sense that you or me, or any other than Parallax start this shuttle if we later don't have the resources start mass production. Parallax can buy from those 100 units at $250 ea, and/or can later start mass-production.
Yes they won't own the GDS file, because baysand will own that. But who cares about the GDSII? ... at submicron levels I think that all foundries take hostages. At 65nm, is it really possible to move one GDSII file from OnSemi to TSMC or to GF and expect it to work without modifications? I am not sure if that is actually possible, and I though that the only exception was between TSMC and UMC.
100% SUCESS.
The P1v has been proven on almost one dozen FPGA (DE-0 nano, Bemicro CV, Pipistrello, ...) and from different vendors (Altera and Xilinx).
So if baysand quotes in its website 'RTL hand off and sign off' and 'BaySand ASIC proven methodology' and 'Customer does not need special tools, licenses, or EDA tools expertise' then the P1v will need to be 100% risk free.
If Salah Werfelli said : "We are excited to introduce this innovative program that will provide access to deep submicron affordable and risk free ASIC"
and we later found that the P1v shrink @65nm didn't succed, then they will need to explain into this public forum what was wrong with their proven methodology.
That is a key question that Parallax will need to negotiate with them. I would expect a P1v to be really small at 65nm, and this will mean lots of dies per wafer and low price. Obviously, if high volume P1v is no less than $12 per die then this shuttle has no real benefit.
Chip said that they seems to be targeted to high-end FPGA who will reduce the bill from >$1k to less than $1k. But did he actually asked them?
So forget all about this idea. As Chip said, they just focus on high-end FPGA.
Basically they are like an FPGA of varying sizes. However the interconnects use metal mask layers rather than gates and ram. It is these metal mask layers that are customised to make our circuit.
Most any circuit working on a Cyclone IV/V will work on their circuit. They have the same I/O structure as the Cyclone IV/V.
Speed is expected to be 2x the FPGA and around 300MHz.
The example chip they quoted is a rather smallish Cyclone IV/V.
Currently only BGA chips are available although they are perhaps interested in making QFP.
From this, you can expect that volume production will not achieve the same pricing as what we expect to see from a custom ASIC like P2. And the I/O will not have analog, etc.
So, for someone wanting a small run of chips for a custom P1 or cutdown P2 design, probably a good WTG. For a P1 or P2 addition/replacement - too expensive.
Not sure how many P1V's and/or P2 cogs would fit (more used to Altera LE's than slices/clb flops etc), but still neat to have that much of a solution available and ready to connect to a bus.