CP2102N improved USB-UART
jmg
Posts: 15,173
SiLabs have released a new CP210x member, an upgrade of the older CP2102 -> CP2102N.
This new one uses a faster MCU core, and adds
* Clock out 48MHz/(2*D) so 6MHz, 4.8MHz, 4MHz etc are possible
* Baud Rate specs faster to 3MBd Duplex, & Baud Granularity improves to 24MHz/N
* Hardware handshake
* Battery charger detect & Current ability flag signals
* Remote Wake-up
* MTP instead of OTP config
* Packages down to 3mm x 3mm
* 3.3V regulator, with 100mA total budget (device itself uses 10~13 mA)
* Lower price 91c/10k
http://www.silabs.com/support/pages/document-library.aspx?p=Interface&f=USBXpress USB Bridges
I think when USB connected, the Clock out is +/- 0.25% FLL locked, otherwise +/- 1.5% . Average is probably PC SysCLK ~ 200ppm.
This should match compact P1 designs nicely, ( Could even Power P1 in most cases ?) and be good for P2 designs that do not need to elevate to HS USB.
This new one uses a faster MCU core, and adds
* Clock out 48MHz/(2*D) so 6MHz, 4.8MHz, 4MHz etc are possible
* Baud Rate specs faster to 3MBd Duplex, & Baud Granularity improves to 24MHz/N
* Hardware handshake
* Battery charger detect & Current ability flag signals
* Remote Wake-up
* MTP instead of OTP config
* Packages down to 3mm x 3mm
* 3.3V regulator, with 100mA total budget (device itself uses 10~13 mA)
* Lower price 91c/10k
http://www.silabs.com/support/pages/document-library.aspx?p=Interface&f=USBXpress USB Bridges
I think when USB connected, the Clock out is +/- 0.25% FLL locked, otherwise +/- 1.5% . Average is probably PC SysCLK ~ 200ppm.
This should match compact P1 designs nicely, ( Could even Power P1 in most cases ?) and be good for P2 designs that do not need to elevate to HS USB.