First, in FEB there was this :
They quietly omit mentioning how large the ROM is, but they do say
"The result is the MCL86, which is basically a 7-instruction, 32-bit micro-sequencer. Some of the micro-sequencer's instructions are specialized so as to allow it to rapidly decode instructions as well as nest function calls. With these seven instructions, I was able to microcode all of the 8086 opcodes in a relatively small number of micro-sequencer clocks."
I see comments saying fhe core needs 100MHz to give 4.77MHz emulation, and another note saying 180MHz spec on Kintex-7 FPGA, indicates 8.586 MHz top speed ( and ~21:1 microcode MHz to CPU MHz )
Updated to mention 4 Blocks for ROM, I think means ~18k Bytes, so quite a bit of 'microcode' ?
and now, there is this
Almost exactly the same LUT count 308 vs 312 for MCL86 vs MCL51, no ROM size mentioned yet.
This says "8-bit controller running at clock speeds from DC to a few megahertz"
"a small demo that instantiates four of these cores to create a quad-core 8051 (just when you think you've heard of everything, right?). It was easy to do, but I thought you might find it interesting that this four-core 8051 actually consumes less logic than a single 8051 core from the major core vendors. This is not surprising as they are logic-based and the MCL51 is micro-sequencer-based. A single MCL51 core is around 312 LUTs, which is a fifth of the size of 8051 cores from these vendors."
A MCL51 core is probably all you need to configure and service a Smart Pin.
Suppose a design was done with 12 P2 COGS and 4 MCL51 COGS, how much more RAM would fit in the space freed by removing the larger COGs ?