They also put a cap at each VCC_Core, which are the 8 caps at each corner diagonal.
Even those have long total traces from Pin-Cap-Gnd, and from gnd-inner pad.
They are on the PCB rear, so do not have to be placed in the corner spaces.
Taking some ball park numbers : at roughly 10nH/cm, and using a 400MHz edge rate, 10mm of added trace adds about 25 ohms of impedance, and 20mA into that gives 500mV of bounce.
The idea is to try not to add any more mm, than the existing direct rats-nest path.
To me that is prettier
There now look to be many outer GND lines that can also feed direct to the inner PAD, you can also keep the outer lines, to make a ground mesh, which can connect better to other elements.
Thinking of reasons why to test this with P2 if it were an easy effort on Chips part down the road. I would not imagine more than 2 cores with 25k LE. It would include 2 Hyperrams, and 2 SPI Quad SRAM 1Mb( http://www.digikey.com/product-detail/en/microchip-technology/23LC1024-I-SN/23LC1024-I-SN-ND/3543084 ). All it does is break out all the IO. SRAM and HyperRam are jumpered to pins or can be patched. I was going to build a few of these in case I need to send a few to some folks to help with Hyperram, Verilog code etc.
Nice work. This looks like it could turn into a useful bare bones board for memory testing with the 10M25 and P1V. Might also be good if you keep the pin headers on a 0.1 inch grid so any other proto boards etc later could be plugged in on top, assuming your USB connector placement doesn't prevent that. From my eyeing of your screen grab it appears some pins are a little bit off the grid. If you lined up the JTAG header pins too, that could be passed through to any board above so it wouldn't have to be occluded, although there should be room for the 10 way JTAG cable to snake through in the lower gap in the pins at the bottom of the board.
Is that a standard 8x10cm sized board?
Cheers,
Roger.
ps. Just noticed and I guess you are still working on it, but some of the main power traces look a bit on the thin side from the input terminal, unless you have separate planes for power that are not shown there.
Thanks rogloh. Correct, there is no effort towards keeping a grid at this point. The first effort is just to get some rough placement on about 5 different boards in the works, then come back for tweaks, groundplane, power traces etc that need to be routed manually. I still have several more boards to get designed and then I can order a large 12"x14" panel with various boards on it. The board is not any standard, it just what worked out in eagle to be the smallest I can make it without spending a lot of time on it due to routing times if you try to go too small. I have never used any proto boards on top and the idea for this was just to have a simple tester and if needed design another board that mounts on top, mating with the headers as they are. However it is easy to go put all headers back on a .1 grid to allow for a generic .1 board to sit on it if you were interested in that. As well, I don't see any real demand for this from the forum so it was not really being considered as a product in and of itself. I would gladly send a few out for no cost if a few of you guys wanted one, as that would really speed up the testing for the ram, sram, etc. For this MAX1025 board, I will put it all on a grid, including the Jtag. I could also add a jumper and horizontal header( .1"? ) for someone using a Propstick, as it currently has a Silabs USB part which I prefer over FTDI and requires my custom proploader. I could leave off the USB veritcal SMT port in that case. My thoughts were that it would be good to put female receptacles on this board, then drop a board on top with male headers on the bottom to make for an easily detachable top board for prototyping. If not prototyping, then just put all headers on it so at least you can connect some test stuff, leds, scope.
Yeah, 0.1 inch sounds good. Also if you bring out the two USB pins as well to pin headers you could even add USB connectors to the proto board above it, though a side mount USB connector would likely prevent any blockage issues there.
On that board, all IO is on the headers. The bottom row shows scl, sda, rx, tx for IO 28, 29, 30, 31. For a propplug, I could put on a separate header for vss, 3v3, rx, tx in the correct order.
On that board, all IO is on the headers. The bottom row shows scl, sda, rx, tx for IO 28, 29, 30, 31. For a propplug, I could put on a separate header for vss, 3v3, rx, tx in the correct order.
A prop plug interface makes sense in case the USB part is not fitted/functional, though I think it is GND, Reset, TX, RX (not sure about the proper order).
If you add the reset line passives and transistor you can also use an FTDI cable instead of prop-plug. I have made my own prop plug this way, but some of that already might be present on your USB interface, depending on your actual design.
The BeMicro MAX 10 board uses a M25P16-VMN6P SPI flash part (2MB) and I think ozpropdev has been able to get it talking to the MAX10 in the boot loader as well. Not sure about any Dual or QSPI capabilities though as I've not played with it myself. I am also not sure how compatible all these different SPI flash parts are, am guessing they are not. Probably choose whatever part the P2 is intending to use if it is stated anywhere.
I will add the flash part, or other memory if there are suggestions for parts you want to test. The pinout may be similar between devices. As for FTDI, I will put in the FT232RL device, with an NPN on RESn, with a mini USB horizontal mount. It will be jumpered to P30/31, so I can use my own USB device externally and you can use FTDI drivers with whatever software IDE. I think the flash can be routed to IO in Verilog so it can be parked on any spare pins right? Even if oz has something working on certain pins for SPI flash boot, it would take a few minutes to change to different IO in Quartus pin assignments.
You might also want to bring up your voltage lines up to any top board too via some additional power pins if that board needs its own supply for special voltages/more current etc.
So far P2 has just used standard flash (not Dual/Quad SPI). However the benefit with FPGA is you can route the two extra pins in case QSPI ever happens
Regarding I2C eeproms (P1, P1V) - even though there is experimentation about including these inside the FPGA memory structure, it still makes sense to put external pads so you can put a standard prop 32kB or 64kB eeprom. You're going to want to bring the I2C pins P28,P29 out anyway.
Many of the dev boards have a really small I2C eeprom. Eg the Bemicro A2: - " -1K (128 x 8) Two-wire Serial EEPROM"
So far P2 has just used standard flash (not Dual/Quad SPI). However the benefit with FPGA is you can route the two extra pins in case QSPI ever happens
Chip has yet to port the SPI boot code for P2, but I think the P2 boot will need to define and control QuadSPI pins, even as single SPI.
That's because those Quad pins are HOLD# and WRP# on Single-SPI parts, and you do not want those floating about - they need to be safely defined (at least pulled up) until you flip over into QuadSPI mode.
P2 Boot does not have to work in Quad, but it needs to be able to start with a Quad-Wired part.
The BeMicro MAX 10 board uses a M25P16-VMN6P SPI flash part (2MB) and I think ozpropdev has been able to get it talking to the MAX10 in the boot loader as well.
This raises a couple of questions -
If the MAX10 board uses 25P16, what is the relative cycle endurance and programming times of MAX10 vs 25P16 ?
It could be a good idea to develop using external memory, if that is faster or saves wear-out of MAX 10 ?
I think it is simpler to have separate boot part, as that avoids clobbering MAX10 code with P1/P2 code, and it means any upcoming MAX10 P2 image can boot using an expected connection part.
ie this means two one SPI Flash parts. (they can be the same part code) One for MAX10, and one for P1/P2
I had put 220k pulldowns for placeholders and also for cases where the jumpers were removed. Easy to change to pullups, but I need to pull all pins to a state on the SRAM, Flash and Hyper. I was using 220k to VSS on all. The eeprom is 64k hardwired to IO 28/29.
In opposite to most FPGAs the Max10 can not boot from an external Flash.
While developing verilog, you can load the new configuration directly to the config-RAM over JTAG, no wear out, and fast.
Writing the internal Flash is so time consuming that you don't want to do it often.
In opposite to most FPGAs the Max10 can not boot from an external Flash.
While developing verilog, you can load the new configuration directly to the config-RAM over JTAG, no wear out, and fast.
Writing the internal Flash is so time consuming that you don't want to do it often.
Oops, OK, then only one SPI memory is needed.
The mention of one on the MAX 10 board had me thinking it was optional-boot use.
Spent a few minutes making the changes. All on a .1 grid. Added M25P16 Flash with jumpers. Changed all pullups to SRAM, HYPER, and FLASH to 220K to 3v3. Will look further to what should be pulled up or down. Added FT2332RL, external header for Tx, Rx, RESn, GND, selectable jumpers. Added 5,3v3,Gnd header to send power up to a board. I like the Molex Minifit JR. header for main power in, this could change as this board is not for my use.
All IO is exposed to headers. Some IO were brought out after the decisions were made for the 64IO p1v set, just to have them available. I tried to put all 64IO as High Speed. They call some IO High Speed, Low Speed. Then there are a number of Vref IO pins with higher capacitance that are on headers just in case they are ever needed. I will work on power traces later.
Advantage of Quad SPI FLASH FT25H16 versus Non quad M25p16?
Once a company has a quad part, you can be sure the older part will fade quickly.
The FT25H16 even beats smaller parts on price, so it pays to check every 6-12 months on the price-minimum point. Right now the TSSOP FT25H16T is ~ 14c/1k
Spent a few minutes making the changes. All on a .1 grid. Added M25P16 Flash with jumpers. Changed all pullups to SRAM, HYPER, and FLASH to 220K to 3v3. Will look further to what should be pulled up or down. Added FT2332RL, external header for Tx, Rx, RESn, GND, selectable jumpers. Added 5,3v3,Gnd header to send power up to a board. I like the Molex Minifit JR. header for main power in, this could change as this board is not for my use.
Looking tidy T Chap, good stuff. You almost have it all fitting within 80mmx100mm by the looks of it which are easy to make in the free version of Eagle. Also often 10x10cm are fairly cheap boards to produce so if you constrain to within those dimensions it may be cheaper.
I use Sunstone and build 12"x14" boards with various designs on it, with stencils made with the order. I make about 6 panels, which will give a number of these MAX10 tester boards. I have a few more designs to complete then I can submit an order in the next few weeks hopefully. I will let you guys know when I have the MAX10 tester board ready and will send a few out so a few of you can be working on it as well. I have eagle pro so I am not trying to fit the free version. I will post the brd if anyone wanted to try to tweak it to fit the free version, but I use an older eagle because I couldn't figure out how to convert my library. It may not load on newer versions unless someone can figure out how to convert it. They tried to explain the process but I didn't get far.
I see Altera have a MAX 10 errata, around power supply ramping.
es_max10.pdf: Long Term Solution
Starting with shipments with date code 1625, MAX 10 devices have a modified power on configuration scheme that enables a simplified power on scheme. This gives you an easier method of configuring MAX 10 devices with the following benefits:
• Single power up scheme
• No power up sequencing requirements
• Maximum power supply rail ramp time increased from 3 ms to 10 ms
• Minimum power supply rail ramp time of 200 μs is now a recommendation rather than an absolute minimum
• No changes to either the die or the ordering part number (OPN)
&
Note:
Ensure that you select the Instant ON POR scheme if you are using a Quartus Prime software version prior to 16.0. If you select Fast POR delay or Slow POR delay, this may result in failure even if the device has a date code of 1625 or later.
that 10ms could need to be checked, especially if you have SMPS with soft-start features.
Comments
Even those have long total traces from Pin-Cap-Gnd, and from gnd-inner pad.
They are on the PCB rear, so do not have to be placed in the corner spaces.
Taking some ball park numbers : at roughly 10nH/cm, and using a 400MHz edge rate, 10mm of added trace adds about 25 ohms of impedance, and 20mA into that gives 500mV of bounce.
The idea is to try not to add any more mm, than the existing direct rats-nest path.
There now look to be many outer GND lines that can also feed direct to the inner PAD, you can also keep the outer lines, to make a ground mesh, which can connect better to other elements.
Nice work. This looks like it could turn into a useful bare bones board for memory testing with the 10M25 and P1V. Might also be good if you keep the pin headers on a 0.1 inch grid so any other proto boards etc later could be plugged in on top, assuming your USB connector placement doesn't prevent that. From my eyeing of your screen grab it appears some pins are a little bit off the grid. If you lined up the JTAG header pins too, that could be passed through to any board above so it wouldn't have to be occluded, although there should be room for the 10 way JTAG cable to snake through in the lower gap in the pins at the bottom of the board.
Is that a standard 8x10cm sized board?
Cheers,
Roger.
ps. Just noticed and I guess you are still working on it, but some of the main power traces look a bit on the thin side from the input terminal, unless you have separate planes for power that are not shown there.
Speaking of P2, do you have a SPI memory to load external P2 from (and P1V, I guess?) eg FT25H16
A prop plug interface makes sense in case the USB part is not fitted/functional, though I think it is GND, Reset, TX, RX (not sure about the proper order).
Any specific IO? Dual or quad.
It does have 64k eeprom already on sda/scl
Regarding I2C eeproms (P1, P1V) - even though there is experimentation about including these inside the FPGA memory structure, it still makes sense to put external pads so you can put a standard prop 32kB or 64kB eeprom. You're going to want to bring the I2C pins P28,P29 out anyway.
Many of the dev boards have a really small I2C eeprom. Eg the Bemicro A2: - " -1K (128 x 8) Two-wire Serial EEPROM"
Chip has yet to port the SPI boot code for P2, but I think the P2 boot will need to define and control QuadSPI pins, even as single SPI.
That's because those Quad pins are HOLD# and WRP# on Single-SPI parts, and you do not want those floating about - they need to be safely defined (at least pulled up) until you flip over into QuadSPI mode.
P2 Boot does not have to work in Quad, but it needs to be able to start with a Quad-Wired part.
If the MAX10 board uses 25P16, what is the relative cycle endurance and programming times of MAX10 vs 25P16 ?
It could be a good idea to develop using external memory, if that is faster or saves wear-out of MAX 10 ?
I think it is simpler to have separate boot part, as that avoids clobbering MAX10 code with P1/P2 code, and it means any upcoming MAX10 P2 image can boot using an expected connection part.
ie this means two one SPI Flash parts. (they can be the same part code)
One for MAX10, and one for P1/P2
Edited as MAX10 cannot FPGA-load from SPI
Google suggests >10k on MAX10, and the 25P16 from Fremont is > 100k rated 85'C
Harder to find Erase/Pgm times ?
While developing verilog, you can load the new configuration directly to the config-RAM over JTAG, no wear out, and fast.
Writing the internal Flash is so time consuming that you don't want to do it often.
Andy
The mention of one on the MAX 10 board had me thinking it was optional-boot use.
All IO is exposed to headers. Some IO were brought out after the decisions were made for the 64IO p1v set, just to have them available. I tried to put all 64IO as High Speed. They call some IO High Speed, Low Speed. Then there are a number of Vref IO pins with higher capacitance that are on headers just in case they are ever needed. I will work on power traces later.
http://www.fremontmicrousa.com/pdf/FT25H16_Rev1.1.pdf
Advantage of Quad SPI FLASH FT25H16 versus Non quad M25p16?
The FT25H16 even beats smaller parts on price, so it pays to check every 6-12 months on the price-minimum point. Right now the TSSOP FT25H16T is ~ 14c/1k
Looking tidy T Chap, good stuff. You almost have it all fitting within 80mmx100mm by the looks of it which are easy to make in the free version of Eagle. Also often 10x10cm are fairly cheap boards to produce so if you constrain to within those dimensions it may be cheaper.
es_max10.pdf:
Long Term Solution
Starting with shipments with date code 1625, MAX 10 devices have a modified power on configuration scheme that enables a simplified power on scheme. This gives you an easier method of configuring MAX 10 devices with the following benefits:
• Single power up scheme
• No power up sequencing requirements
• Maximum power supply rail ramp time increased from 3 ms to 10 ms
• Minimum power supply rail ramp time of 200 μs is now a recommendation rather than an absolute minimum
• No changes to either the die or the ordering part number (OPN)
&
Note:
Ensure that you select the Instant ON POR scheme if you are using a Quartus Prime software version prior to 16.0. If you select Fast POR delay or Slow POR delay, this may result in failure even if the device has a date code of 1625 or later.
that 10ms could need to be checked, especially if you have SMPS with soft-start features.