Or put a pin header layout too so you could add a RAM daughter board later if you figure out the BGA. There may be a BGA adapter board. I have not tried this, but if you could put an array of vias at 1mm pitch, you may be able to use solder spheres and flux. I just searched and I see adapter boards that appear to be doing something similar. Flux holes the solder balls in place.
I think the SQI chip could be replaced with an SPI flash chip for testing boot code, right?
You mean on the main boards ? Some may prefer to not attack their main PCBs ?
A plug-in like you have, is a nice way to flip brands among the 'usual suspects' of Fremont, ISSI, Winbond, Adesto...
Boot read should be portable, however boot-write may need more finesse, and the most flexible would be to make the PC-SPI boot link more open, so the PC sends commands.
That Shifts any revisions to the PC side, and keeps the ROM stable and small.
I haven't followed closely enough to know the history. But I would have expected parts at digikey/mouser by now. Jmg highlighted these quite some time ago.
It's not just the P2 that has roll-out delays
It's been years since Altera announced Stratix 10 and I can find no indication that parts are available, yet. I suspect that when they become available, they will cost, at least, $10k. Altera belongs to Intel now and the Stratix 10 is reliant upon the Intel 14nm Tri-Gate process. Altera's tagline for Stratix 10 was (is?), "Delivering the Unimaginable". They were talking about fabric speeds of 400MHz and "millions" of logic elements. Lots of RAM and DSP blocks, too. It would be great to be able to use those chips for development, but we're already fortunate to have the Cyclone V -A9 available for $230 and covered by the free version of Quartus. We're rich!!!
Now that I think about it perhaps the data lines should be same length.
Yes, 2 layers should be ok.
I would focus on the decoupling caps, and move them right up against the package, and add some underneath, with a focus on shortest total lead length to BGA balls.
Data line Lead-length matching is not super important at P1, P2 speeds.
eg google finds (152.4 mm/ns)
I've been reading about how to do BGA a bit today.
Maybe it's not so bad with this one. There's not so many balls and the spacing is pretty large at 1 mm.
Tubular got it with 2 layers, which helps a lot.
I've decided that I can put vias in the center space between balls as fab place allows standard via holes down to 8 mil.
If you did want to try XIP, on P2, then you might do 1 x HyperFLASH for Code, and 1 x HyperRAM for Graphics & RAM, on two ports.
XIP on P2? Can P2 execute code from external memory? Or are you talking about some sort of LMM/XMM thing?
Should that be XIMMP or XMMIP ?
Yes, some simple cache scheme would be required for P2, but the burst flow rates can be quite high, & skip-coded code can co-operate well with such a cache. As well as Byte Code / LMM etc, I think native binaries are also possible.
Ballpark numbers are burst speeds of just under 40/80/160 Longs every 4us.
Routines that were small enough to fit within that block (or a COG-LUT-expanded version?) could be served the binary once, and then execute inside P2 at full speed.
ie Is that a sort of dynamic fcache ?
The 4us break requirement means a full COG code fetch would need maybe 16us ?
I've been reading about how to do BGA a bit today.
Maybe it's not so bad with this one. There's not so many balls and the spacing is pretty large at 1 mm.
Tubular got it with 2 layers, which helps a lot.
I've decided that I can put vias in the center space between balls as fab place allows standard via holes down to 8 mil.
Sounding good
Can you fit two, to allow 16 wide testing ?
Digikey shows 3v parts due on 25th May and Mouser shows on 13 June.
I think it will be fine with just 24 balls. I can imagine why they have to xray once they have hundreds of balls though.
OSHpark 4 layer may even be ok at 0.8mm pitch if you shrink the pads to 0.42mm instead of 0.5mm.
Digikey put the waiting time (was 5/25) on the 3v Hyperram right out yesterday, and Mouser's stock hasn't come in. Given the only stock anywhere searchable of any of they HyperRam variants is the 37 pcs of 1v8 at digikey, I'm going to order some of those. Anyone else interested might like to do the same before they run out
Testing 1v8 HyperRam with a P1V is no problem, since a bank of 16 gpio can be set to 1v8. Testing with a P1 at 1v8 at ~1.95v should be fine too, I think the PLL worked down to around 1v7 but need to get up to speed on all that again.
Testing with a P2 might be possible on the P123-A7 boards which has the settable PCIe connector, but would be tricky on the A9.
The absolute max on those chips seems a blanket 4.0 volts, which seems high, and perhaps the 1v8 can be operated at higher voltages than 1.95 if necessary with the P1.
The other difference with the 1v8 Hyperram is the need for the CK#. That'd be an extra pin needed vs what I designed earlier, Ray
I think I might make an adapter that adapts TSSOP-54 to the hyper-ram. I can then use it with my P1V stamp, which would struggle otherwise
I've been reading about how to do BGA a bit today.
Maybe it's not so bad with this one. There's not so many balls and the spacing is pretty large at 1 mm.
Tubular got it with 2 layers, which helps a lot.
I've decided that I can put vias in the center space between balls as fab place allows standard via holes down to 8 mil.
Sounding good
Can you fit two, to allow 16 wide testing ?
addit...
In addition to 2 x HyperRAM, adding these parts allows RWDS to generate a LCD_CLK for LCD streaming testing. (74AUP1G57 ( SOT26), 2k2, 10pF )
HyperRAM DDR ClkOUT to LCD Doubler
1,3 __ 5
RWDS--o----------\\ \
| ___ || |o----- LCD_CK
+-|___|--o-//__/ 4 ==\_/== per edge in
R |6 2
| 74AUP1G57
C --- XNOR connected
---
|
GND or VCC
eg 20M DDR in to 40M LCD_CK (P1 possible)
Delay from RC appx 25ns
Measure & trim, as Hyst and swing effects etc
complicate any exact calcs
Start with 2k2, 10pF
(created by AACircuit v1.28.6 www.tech-chat.de)
That'd be no trouble to add jmg, but we can already generate 40M ok on P1 using the counters. I'm sure I'm missing something...
Yup, you can, but the RWDS is phase correct and it starts wiggling when valid data comes out of HyperRAM. (and it pauses, if Data ever pauses)
It probably is possible to generate the 20M DDR HR clock, and then precisely delay and start the 40M LCD_CLK right when HyperRAM data is due, but XNOR to me is simpler to debug.
A very simple rapid P1 test would be to connect a LCD and frame it up, then Clock.
(no writes yet..)
The displayed random noise should be stable, if refresh is correct.
3v HyperRAM is due tomorrow at Digikey, but I see someone has already taken 30 from the 100 arriving. (perhaps someone from here ? )
Anyone wanting these best not delay. Next drop is August !
Comments
https://www.ironwoodelectronics.com/press/chip_size_linear_socket.cfm
http://www.proto-advantage.com/store/images/PRODUCTS/BGA0011_0.JPG?osCsid=ib26oooqj9vanu5abkhq3rsov7
Another footprint request would be TSSOP8 to allow full qualify of Serial Flash Boot code.
This one has an impressive price & is in stock :
SERIAL FLASH 16M-BIT 120MHz TSSOP8 FT25H16T-RB 1,000 $0.13860
http://www.digikey.com/product-detail/en/fremont-micro-devices-usa/FT25H16T-RB/1219-1195-ND/5875689
I used 6 mil track and space but only 2 layers
Now that I think about it perhaps the data lines should be same length.
Hopefully this could also be used with quickstart, upside down, and by running a few voltage wires up to the other end of the header
[img][/img]
You mean on the main boards ? Some may prefer to not attack their main PCBs ?
A plug-in like you have, is a nice way to flip brands among the 'usual suspects' of Fremont, ISSI, Winbond, Adesto...
Boot read should be portable, however boot-write may need more finesse, and the most flexible would be to make the PC-SPI boot link more open, so the PC sends commands.
That Shifts any revisions to the PC side, and keeps the ROM stable and small.
It's been years since Altera announced Stratix 10 and I can find no indication that parts are available, yet. I suspect that when they become available, they will cost, at least, $10k. Altera belongs to Intel now and the Stratix 10 is reliant upon the Intel 14nm Tri-Gate process. Altera's tagline for Stratix 10 was (is?), "Delivering the Unimaginable". They were talking about fabric speeds of 400MHz and "millions" of logic elements. Lots of RAM and DSP blocks, too. It would be great to be able to use those chips for development, but we're already fortunate to have the Cyclone V -A9 available for $230 and covered by the free version of Quartus. We're rich!!!
I would focus on the decoupling caps, and move them right up against the package, and add some underneath, with a focus on shortest total lead length to BGA balls.
Data line Lead-length matching is not super important at P1, P2 speeds.
eg google finds (152.4 mm/ns)
Maybe it's not so bad with this one. There's not so many balls and the spacing is pretty large at 1 mm.
Tubular got it with 2 layers, which helps a lot.
I've decided that I can put vias in the center space between balls as fab place allows standard via holes down to 8 mil.
XIP on P2? Can P2 execute code from external memory? Or are you talking about some sort of LMM/XMM thing?
Should that be XIMMP or XMMIP ?
Yes, some simple cache scheme would be required for P2, but the burst flow rates can be quite high, & skip-coded code can co-operate well with such a cache. As well as Byte Code / LMM etc, I think native binaries are also possible.
Ballpark numbers are burst speeds of just under 40/80/160 Longs every 4us.
Routines that were small enough to fit within that block (or a COG-LUT-expanded version?) could be served the binary once, and then execute inside P2 at full speed.
ie Is that a sort of dynamic fcache ?
The 4us break requirement means a full COG code fetch would need maybe 16us ?
Sounding good
Can you fit two, to allow 16 wide testing ?
Digikey shows 3v parts due on 25th May and Mouser shows on 13 June.
I think it will be fine with just 24 balls. I can imagine why they have to xray once they have hundreds of balls though.
OSHpark 4 layer may even be ok at 0.8mm pitch if you shrink the pads to 0.42mm instead of 0.5mm.
Digikey put the waiting time (was 5/25) on the 3v Hyperram right out yesterday, and Mouser's stock hasn't come in. Given the only stock anywhere searchable of any of they HyperRam variants is the 37 pcs of 1v8 at digikey, I'm going to order some of those. Anyone else interested might like to do the same before they run out
Testing 1v8 HyperRam with a P1V is no problem, since a bank of 16 gpio can be set to 1v8. Testing with a P1 at 1v8 at ~1.95v should be fine too, I think the PLL worked down to around 1v7 but need to get up to speed on all that again.
Testing with a P2 might be possible on the P123-A7 boards which has the settable PCIe connector, but would be tricky on the A9.
The absolute max on those chips seems a blanket 4.0 volts, which seems high, and perhaps the 1v8 can be operated at higher voltages than 1.95 if necessary with the P1.
The other difference with the 1v8 Hyperram is the need for the CK#. That'd be an extra pin needed vs what I designed earlier, Ray
I think I might make an adapter that adapts TSSOP-54 to the hyper-ram. I can then use it with my P1V stamp, which would struggle otherwise
In addition to 2 x HyperRAM, adding these parts allows RWDS to generate a LCD_CLK for LCD streaming testing. (74AUP1G57 ( SOT26), 2k2, 10pF )
HyperRAM DDR ClkOUT to LCD Doubler 1,3 __ 5 RWDS--o----------\\ \ | ___ || |o----- LCD_CK +-|___|--o-//__/ 4 ==\_/== per edge in R |6 2 | 74AUP1G57 C --- XNOR connected --- | GND or VCC eg 20M DDR in to 40M LCD_CK (P1 possible) Delay from RC appx 25ns Measure & trim, as Hyst and swing effects etc complicate any exact calcs Start with 2k2, 10pF (created by AACircuit v1.28.6 www.tech-chat.de)Yup, you can, but the RWDS is phase correct and it starts wiggling when valid data comes out of HyperRAM. (and it pauses, if Data ever pauses)
It probably is possible to generate the 20M DDR HR clock, and then precisely delay and start the 40M LCD_CLK right when HyperRAM data is due, but XNOR to me is simpler to debug.
A very simple rapid P1 test would be to connect a LCD and frame it up, then Clock.
(no writes yet..)
The displayed random noise should be stable, if refresh is correct.
Anyone wanting these best not delay. Next drop is August !