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Extreme signalling — Parallax Forums

Extreme signalling

Marcus76Marcus76 Posts: 25
in Propeller 2
There has been a lot of discussion in the LUT thread about high-speed high-throughput communication and whether or not it is important for the P2. I am curious about what the most extreme case of signaling is that the finished P2 will actually be able to handle. There has been some criticism of looking at extreme cases, so I will clarify that what I am asking is not necessarily a practical application, but is just for curiosity.

One case of extreme communications that does not have a useful slow speed fallback is PCI express. Consider the finished P2 running at 200MHz (IIRC the proposed speed), and 7400 series logic capable of running at 100MHz (one of the high-speed families), can the P2 be made to do some simple non-trivial task over PCIe?

My thought was that you can use parallel-to-serial shift registers to output to the PCIe bus, and serial-to-parallel to input from the bus. So you have, for example, 8 pins on the P2 outputting at 12.5MHz into an 8-bit shift register that shifts out at 100MHz to some circuit that drives the bus. You could vary that to be, e.g. 16 or 24 pins if you can't keep up at 8. Do you think that this would be feasible?

Comments

  • jmgjmg Posts: 15,173
    edited 2016-05-15 21:14
    Marcus76 wrote: »
    So you have, for example, 8 pins on the P2 outputting at 12.5MHz into an 8-bit shift register that shifts out at 100MHz to some circuit that drives the bus. You could vary that to be, e.g. 16 or 24 pins if you can't keep up at 8. Do you think that this would be feasible?
    Using 7400 Logic, no.

    I'm not clear what you are trying to do exactly, but this
    https://en.wikipedia.org/wiki/PCI_Express
    shows the simplest PCIe has 2.5 GT/s for Data of 250 MB/s

    That makes it similar to HDMI, which needs at the very least an external PHY+Serialize device.

    Sounds like 16b Clocked at 125MHz could match that speed, but simpler may be the FT600, which does USB 3,
    and has the FIFO and PHY all included, and is more main stream than PCIe, for similar speeds.

    The FT600 has 100MHz or 66MHz FIFO interface, and a choice of 16b or 32b wide.

    The P2 Streamer may be able to cope, with raw data rates, but the details matter.

    My questions are still open around the PLL, and if it can use that 66/100MHz clock from FT600, instead of the usual Crystal.
    You can of course Clock the P2 directly, which limits core speed to 66 or 100MHz.

    An alternative, would be to use the Si5351, to requalify that 66/100MHz to 132 or 198 or 200MHz, and the Si5351 does have a Phase option, which is likely to be needed to correctly align the P2 streamer edges, with the FT600 slots.

    Then there are the details of the handshakes.
    In theory, P2 may be able to connect to a FT600, with minor fixes to the possible handshake details.

  • Marcus76Marcus76 Posts: 25
    Oops. I was looking at the reference clock (100MHz) and not the data rate (for some reason), so my original post doesn't make any sense. NXP's logic selection guide lists 7400 series shift registers with a fmax of 180MHz (LVC family). It seems odd to me that modern high-speed buses are operating at an order of magnitude higher frequency than the highest rate for discrete logic. You could still use the shift register trick to talk to buses that are fast for the P2. PCIe et al requiring specialized hardware takes a lot of the fun out of these sort of hacks.
  • jmgjmg Posts: 15,173
    Marcus76 wrote: »
    Oops. I was looking at the reference clock (100MHz) and not the data rate (for some reason), so my original post doesn't make any sense. NXP's logic selection guide lists 7400 series shift registers with a fmax of 180MHz (LVC family). It seems odd to me that modern high-speed buses are operating at an order of magnitude higher frequency than the highest rate for discrete logic. You could still use the shift register trick to talk to buses that are fast for the P2. PCIe et al requiring specialized hardware takes a lot of the fun out of these sort of hacks.
    Certainly discrete logic is off the table, but they do make shift registers that take parallel data and send out the LVDS type high speed cable info.

    The FT600 to me looks one of the better choices, for highest-possible P2 transfer speeds.
    More modest may be 100M Ethernet, which uses a PHY with 25MHz nibble rates.
    Again, the streamer can do 25MHz nibbles, but the details are not proven for Ethernet yet.

  • guenthertguenthert Posts: 36
    Marcus76 wrote: »
    It seems odd to me that modern high-speed buses are operating at an order of magnitude higher frequency than the highest rate for discrete logic.
    Why? It must be some twenty years since there were discrete logic chips anywhere near the main bus of a PC.
  • kwinnkwinn Posts: 8,697
    Marcus76 wrote: »
    Oops. I was looking at the reference clock (100MHz) and not the data rate (for some reason), so my original post doesn't make any sense. NXP's logic selection guide lists 7400 series shift registers with a fmax of 180MHz (LVC family). It seems odd to me that modern high-speed buses are operating at an order of magnitude higher frequency than the highest rate for discrete logic. You could still use the shift register trick to talk to buses that are fast for the P2. PCIe et al requiring specialized hardware takes a lot of the fun out of these sort of hacks.

    Not so surprising that circuits using discrete logic chips like the 7400 series are slower comparable circuitry on a single chip. Simple physics. The speed of light in a vacuum is approximately 300,000,000 meters/second, and electrons in a circuit travel a bit slower than that. In one nanosecond a signal travels less than 0.3 meters, or about 1 foot. There is a very good reason the early Cray supercomputers placed the circuit boards radially and had the bus and interconnects in the central hollow core.
  • Marcus76Marcus76 Posts: 25
    There are two kinds of "speed" here: frequency and latency. If you are making a complex circuit in discrete logic then the latency in that circuit will limit the frequency. If you have a very simple circuit, then the addition to the bus will just add a bit of latency to the round trip time. The things stopping you from making a high-frequency discrete logic family are parasitics. Granted, the high-frequency buses have much more complex signaling that makes the utility of high-frequency discrete logic pretty limited, but it seems like there would be enough odd niche applications that you would see a logic family made for it.
  • jmgjmg Posts: 15,173
    Marcus76 wrote: »
    ... but it seems like there would be enough odd niche applications that you would see a logic family made for it.

    You are right, and there is
    http://www.analog.com/en/products/high-speed-logic.html

    - You can even buy some off the shelf, take a look at :
    http://www.mouser.com/Analog-Devices-Hittite/Semiconductors/Logic-ICs/_/N-4s5z6?P=1yuv9ai
  • kwinnkwinn Posts: 8,697
    jmg wrote: »
    Marcus76 wrote: »
    ... but it seems like there would be enough odd niche applications that you would see a logic family made for it.

    You are right, and there is
    http://www.analog.com/en/products/high-speed-logic.html

    - You can even buy some off the shelf, take a look at :
    http://www.mouser.com/Analog-Devices-Hittite/Semiconductors/Logic-ICs/_/N-4s5z6?P=1yuv9ai

    Yep, and be sure to check the pricing before you order a bunch.
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