P2 PLL and external Clock details
jmg
Posts: 15,173
in Propeller 2
From other thread.. looking at using P2 with Fast parallel modes in FIFO HS USB Devices, for high USB transfer rates:
FT2232H gives these specs
Async: * USB to parallel FIFO (async) transfer data rate up to 10Mbyte/sec.
In pure bit-bang mode, this is a repeating
Test_Handshake
Put Data
WRN=L
WRN=H
Test_Handshake
RDN=L
Get Data
RDN=H
What SysCLK is needed, for this loop to hit 10MHz, rolled and unrolled ?
Does REP opcode allow WAIT ?
However, there is already a pulse mode in Smart pins, - could that trigger from the Adjacent pin Access ?
(this would mean WRN and RDN are close enough to use the A,B reach fields)
This effectively creates a new Strobed-opcode, that could almost double the software-based IO speed.
Test_Handshake
Put Data(Strobe)
Test_Handshake
Get Data(Strobe)
Then we have HS USB device Sync modes, which can run up to 4x faster, with more constraints.
Sync: * Single channel synchronous FIFO mode for transfers up to 40 Mbytes/sec.
The FT2232H Sync mode outputs a 60MHz clk.
FT600 generates the same 60 or 100MHz clock out, that all data needs to align to.
Operational choice look to be
a) Clock the P2 directly from that eCLK (60/100MHz)
I think the P2 can accept an external clock at those speeds ? No change needed.
b) Use that 60MHz to sync the PLL, to 120MHz or 180MHz ? (better matches target chip speeds)
Can the present P2 PLL design manage that ? - I think maybe dividers need improving ?
There may also be general cases, where the PLL is needed to software-lock to the external reference edge.
This could be done with a Wait edge but can that map onto the Xtal/ExtCLK signal ?
To use Sync modes, the P2 also needs to be able to generate pulses down to 1/eCLK.
Classic Pin-bash does not do that at 60MHz, (needs 120MHz?), but the Smart Pin Strobed opcode modes above, could generate single clk strobes.
It seems 20-30M Strobes/sec may be possible, in a SW-HW co-operate system ?
That covers 8/16/32b device widths, for close to 100MBytes/sec speeds with FT600 ?
FT2232H gives these specs
Async: * USB to parallel FIFO (async) transfer data rate up to 10Mbyte/sec.
In pure bit-bang mode, this is a repeating
Test_Handshake
Put Data
WRN=L
WRN=H
Test_Handshake
RDN=L
Get Data
RDN=H
What SysCLK is needed, for this loop to hit 10MHz, rolled and unrolled ?
Does REP opcode allow WAIT ?
However, there is already a pulse mode in Smart pins, - could that trigger from the Adjacent pin Access ?
(this would mean WRN and RDN are close enough to use the A,B reach fields)
This effectively creates a new Strobed-opcode, that could almost double the software-based IO speed.
Test_Handshake
Put Data(Strobe)
Test_Handshake
Get Data(Strobe)
Then we have HS USB device Sync modes, which can run up to 4x faster, with more constraints.
Sync: * Single channel synchronous FIFO mode for transfers up to 40 Mbytes/sec.
The FT2232H Sync mode outputs a 60MHz clk.
FT600 generates the same 60 or 100MHz clock out, that all data needs to align to.
Operational choice look to be
a) Clock the P2 directly from that eCLK (60/100MHz)
I think the P2 can accept an external clock at those speeds ? No change needed.
b) Use that 60MHz to sync the PLL, to 120MHz or 180MHz ? (better matches target chip speeds)
Can the present P2 PLL design manage that ? - I think maybe dividers need improving ?
There may also be general cases, where the PLL is needed to software-lock to the external reference edge.
This could be done with a Wait edge but can that map onto the Xtal/ExtCLK signal ?
To use Sync modes, the P2 also needs to be able to generate pulses down to 1/eCLK.
Classic Pin-bash does not do that at 60MHz, (needs 120MHz?), but the Smart Pin Strobed opcode modes above, could generate single clk strobes.
It seems 20-30M Strobes/sec may be possible, in a SW-HW co-operate system ?
That covers 8/16/32b device widths, for close to 100MBytes/sec speeds with FT600 ?