I just noticed some emails from earlier today where Treehouse is coordinating with OnSemi to get the test chip GDS file to them tomorrow. The shuttle is starting on Monday.
I just noticed some emails from earlier today where Treehouse is coordinating with OnSemi to get the test chip GDS file to them tomorrow. The shuttle is starting on Monday.
From there, what is the time line to first numbers ?
I can't find any pin description of this test chip, or a datasheet. Is there one?
Kind regards, Samuel Lourenço
This is not a chip that can be used by anyone outside of Parallax. It is just to verify the analog portions of the P2 chip. There are no COGs or any ability to run code on it as far as I know.
I can't find any pin description of this test chip, or a datasheet. Is there one?
Kind regards, Samuel Lourenço
This is not a chip that can be used by anyone outside of Parallax. It is just to verify the analog portions of the P2 chip. There are no COGs or any ability to run code on it as far as I know.
Thanks David. I'm aware that this is just the IO portion of two pins. I asked out of curiosity, as I would like to see what each pin does. I'm assuming this is an open design, correct?
Thanks David. I'm aware that this is just the IO portion of two pins.
I thought it was a full Pad Count test, of basically all the non-verilog parts of P2 ?
ie it is to test ADC/DAC/PLL and full layout ?
I think there are limits on connections, but hopefully all pins can be tested, if only 2 at a time.
FWIR, it is strangely not going into the final P2 package, which means ground effects will differ.
I also have some reservations about limitations on the PLL, as the VCO dividers are hard coded in the Ring.
Smarter to me is to have just the Analog sections (VCO & PFC) in the ring, and the Dividers(VCO & Ref) in Verilog.
I've received notification that the shuttle will finish on 9/22, or in about one more month. This has been a really long time, since we did the tapeout in late May.
This test chip just covers the I/O pins, clock pins, reset pin and test pin input, along with the power pins. There are TWO I/O pins on this chip, so that we can test out things like USB.
Here is the bond diagram I made the other day, which I sent to OnSemi:
It was intended for an 80-pin package, which OnSemi didn't have available for shuttle packaging, so I remapped it to that dual-row QFN. Here are the pins, as planned for the 80-pin package:
Thanks David. I'm aware that this is just the IO portion of two pins.
I thought it was a full Pad Count test, of basically all the non-verilog parts of P2 ?
ie it is to test ADC/DAC/PLL and full layout ?
er to me is to have just the Analog sections (VCO & PFC) in the ring, and the Dividers(VCO & Ref) in Verilog.
...
I recognize P0 and P1 as GPIOs. The rest of them are control pins. I recall that each smart pin block manages two GPIO pins, so makes sense. But I'm just inferring.
I've received notification that the shuttle will finish on 9/22, or in about one more month. This has been a really long time, since we did the tapeout in late May.
This test chip just covers the I/O pins, clock pins, reset pin and test pin input, along with the power pins. There are TWO I/O pins on this chip, so that we can test out things like USB.
Here is the bond diagram I made the other day, which I sent to OnSemi:
It was intended for an 80-pin package, which OnSemi didn't have available for shuttle packaging, so I remapped it to that dual-row QFN. Here are the pins, as planned for the 80-pin package:
I hope that such dual row solution is not to be implemented on the P2. Doing layout for dual row QFNs presents a challenge, as it requires "finer" DRC rules that most board houses won't support. Also, they are harder to solder and impossible to inspect, unless you have an X-ray machine. Even normal QFNs would be quite a no for me, especially if the pitch is 0.5mm or smaller.
Chip,
Any reason given for it taking so long? Or was the start delayed?
I don't know why this has been so slow-going, but it was free. One more month.
Well, that may mean that the P2 will not be ready this year.
I would be happy with Q1-2017 and absolutely ecstatic if I could get one for Christmas.
If it takes 4 months to get a chip after submitting it to tapeout the P2 would have to go into tapeout next week in order to get it by Christmas. And that doesn't include the time for Chip to test the P2 to make sure it works correctly. So I wouldn't hold out too much hope for this Christmas, or even Q1-2017. However, Christmas of 2017 seems like a possibility. Only 492 days until ChipMas!
Time for a new countdown, Dave. I miss your little calendars. Visual aids of a sort, they were. Just need a new target date. How about June 1st, 2017, or June 21st, the start of summer? Those sound reasonable (unless a shuttle fails). I can hear Chip or Ken now, "No more countdowns until we have samples in hand." But countdowns have utility: they can keep things moving forward.
Anyway, now that the design is nearly wrapped up, it's easier to wait (not that we want to push the release back any further, since time marches on and the world with it). We all have things to do while development goes forward. Of course, there's testing to do, but I meant that we can work on other things and continue using the P1. It's not like we've been trapped in an airplane on the tarmac for 12 hours with no idea when we'll take off or be let out (I guess there are laws against that nowadays in the US).
Being trapped like that would drive me out of my mind, unless possibly I had access to the Internet or someone like Chip was sitting next to me and explaining his physical currency (Sorry, just watched a documentary on Sundance about Bitcoin, so currency was on my mind). In many ways, Propeller chips are coins of a sort for Parallax. Now their currency could be hot dogs or whatever, but it's chips. Of course, they make and sell other things, too, and for more money, but making chips seems more similar to minting coins. Now, of course, if the world's currencies collapsed, I'd opt for the hot dogs. But right now (having just eaten), I'm more hungry for some P2's to sink my teeth into, and chips don't have those nasty nitrates. Yes, I'll have an order of P2's and a side order of P1's, thank you. Okay, after reading this, now we're just that much closer to silicon.
The last we heard the shuttle is scheduled to finish on 9/22, which is less than a week now. Looking forward to seeing the results from the test chip.
Me, too! I think they bumped it out to the 29th, last I heard. There is packaging to be done by them, also. I don't know if that adds time. I need to get a board designed. They didn't have any 80-pin package, like I had planned for, so they're going to put it into a dual-row QFN-100. Here's the bond diagram for it:
... I need to get a board designed. They didn't have any 80-pin package, like I had planned for, so they're going to put it into a dual-row QFN-100. Here's the bond diagram for it:
Hmm.. Small, but not so easy to work with in small volumes. Could be fun mounting that in a lab...
Idea: Is that also a possible smaller package for the final P2 ? (ie in addition to TQFP100)
It would shrink size-important P2 designs, to same size as P1.
... I need to get a board designed. They didn't have any 80-pin package, like I had planned for, so they're going to put it into a dual-row QFN-100. Here's the bond diagram for it:
Hmm.. Small, but not so easy to work with in small volumes. Could be fun mounting that in a lab...
Idea: Is that also a possible smaller package for the final P2 ? (ie in addition to TQFP100)
It would shrink size-important P2 designs, to same size as P1.
Well, the die is 8.5 x 8.5mm - same as the package.
Comments
From there, what is the time line to first numbers ?
If nothing else I'm pretty sure you could sell a 'smartpin ring' that would work with other processors and give them super powers
Kind regards, Samuel Lourenço
Maybe a smart coprocessor?
Oops, the other interpretation is it takes 12-14 weeks for a shuttle run.
I can't find any pin description of this test chip, or a datasheet. Is there one?
Kind regards, Samuel Lourenço
Kind regards, Samuel Lourenço
I thought it was a full Pad Count test, of basically all the non-verilog parts of P2 ?
ie it is to test ADC/DAC/PLL and full layout ?
I think there are limits on connections, but hopefully all pins can be tested, if only 2 at a time.
FWIR, it is strangely not going into the final P2 package, which means ground effects will differ.
I also have some reservations about limitations on the PLL, as the VCO dividers are hard coded in the Ring.
Smarter to me is to have just the Analog sections (VCO & PFC) in the ring, and the Dividers(VCO & Ref) in Verilog.
This test chip just covers the I/O pins, clock pins, reset pin and test pin input, along with the power pins. There are TWO I/O pins on this chip, so that we can test out things like USB.
Here is the bond diagram I made the other day, which I sent to OnSemi:
It was intended for an 80-pin package, which OnSemi didn't have available for shuttle packaging, so I remapped it to that dual-row QFN. Here are the pins, as planned for the 80-pin package:
I hope that such dual row solution is not to be implemented on the P2. Doing layout for dual row QFNs presents a challenge, as it requires "finer" DRC rules that most board houses won't support. Also, they are harder to solder and impossible to inspect, unless you have an X-ray machine. Even normal QFNs would be quite a no for me, especially if the pitch is 0.5mm or smaller.
Kind regards, Samuel Lourenço
The P2 package is chosen already, as 100 pin TQFP (gull wing) with thermal Pad, 0.5mm lead pitch.
Any reason given for it taking so long? Or was the start delayed?
I don't know why this has been so slow-going, but it was free. One more month.
I would be happy with Q1-2017 and absolutely ecstatic if I could get one for Christmas.
Anyway, now that the design is nearly wrapped up, it's easier to wait (not that we want to push the release back any further, since time marches on and the world with it). We all have things to do while development goes forward. Of course, there's testing to do, but I meant that we can work on other things and continue using the P1. It's not like we've been trapped in an airplane on the tarmac for 12 hours with no idea when we'll take off or be let out (I guess there are laws against that nowadays in the US).
Being trapped like that would drive me out of my mind, unless possibly I had access to the Internet or someone like Chip was sitting next to me and explaining his physical currency (Sorry, just watched a documentary on Sundance about Bitcoin, so currency was on my mind). In many ways, Propeller chips are coins of a sort for Parallax. Now their currency could be hot dogs or whatever, but it's chips. Of course, they make and sell other things, too, and for more money, but making chips seems more similar to minting coins. Now, of course, if the world's currencies collapsed, I'd opt for the hot dogs. But right now (having just eaten), I'm more hungry for some P2's to sink my teeth into, and chips don't have those nasty nitrates. Yes, I'll have an order of P2's and a side order of P1's, thank you. Okay, after reading this, now we're just that much closer to silicon.
Me, too! I think they bumped it out to the 29th, last I heard. There is packaging to be done by them, also. I don't know if that adds time. I need to get a board designed. They didn't have any 80-pin package, like I had planned for, so they're going to put it into a dual-row QFN-100. Here's the bond diagram for it:
Idea: Is that also a possible smaller package for the final P2 ? (ie in addition to TQFP100)
It would shrink size-important P2 designs, to same size as P1.
Well, the die is 8.5 x 8.5mm - same as the package.