Why 180nm?
samuell
Posts: 554
Hi all,
I wanted to ask this. I see that the P2 will be fabricated using a 180nm process. What I want to ask is, why the need of such a small process. Is it a matter of speed? Or it is just the scale?
I'm concerned, because the smaller the process is, the less robust the silicon is, particularly when talking about ESD and transients. I think there is much hype when people talk about smaller processes as being superior (I think this comes from the advertising around processors, eg, look at the new 28nm CPU, it is a lot faster).
Kind regards, Samuel Lourenço
I wanted to ask this. I see that the P2 will be fabricated using a 180nm process. What I want to ask is, why the need of such a small process. Is it a matter of speed? Or it is just the scale?
I'm concerned, because the smaller the process is, the less robust the silicon is, particularly when talking about ESD and transients. I think there is much hype when people talk about smaller processes as being superior (I think this comes from the advertising around processors, eg, look at the new 28nm CPU, it is a lot faster).
Kind regards, Samuel Lourenço
Comments
A chip can be as robust as you want to design it to be, even at 28nm. There are thicker oxides and larger spacing rules for I/O transistors on small-geometry processes, which connect to the outside world.
It would be great to go to 28nm, but it would cost millions of dollars, whereas 180nm is going to cost us $250k, including synthesis and initial production fabrication.
I see there are economic reasons. But does it means that the P2 will eventually be fabricated using a smaller process? That worries me, especially when I'm concerned about longevity/durability.
Altera FPGAs are the toughest chips I've ever worked with and they are in leading-edge processes. Maybe the complaint is that ESD structures can't be scaled with process, so they remain large.
I hope we could use smaller/faster processes in the future.
Is electromigration a concern?
Source:
https://en.wikipedia.org/wiki/Electromigration
https://en.wikipedia.org/wiki/List_of_semiconductor_scale_examples
... Perhaps, but I don't really think so... the first line of attack as far as ESD structure design can actually be built vertically in most processes... I'm talking about the "comb" structures that create a controlled spark gap.
Typically they are constructed on a 2D horizontal plane, but they can also be constructed vertically.
As far as one process versus another ...
It might simply be a cost alignment wager that determines 180nm to another... if you look at it from the perspective of density verses cost, the comparison is pretty interesting and while you might come out ahead using a smaller process with more density, the initial smack in the wallet is something that must be considered.
Just an FYI : It takes about 3 Volts potential to jump 1 micron .... or in 30kV per cm .... So you can purposefully design an ESD structure that acts more like a Zener voltage regulator/clamp with completely passive structures. Once the "danger voltage" is down to a manageable level a fast switching transistor can further clamp the remaining voltage spike so that internal circuitry is less likely to become damaged from an ESD event.
All the metal, except what is exposed as pads, is encased in dielectric material which inhibits arcing. In the ESD structures that you laid out, there was a lack of silicide implant in the big, multi-fingered ESD-clamp FET drains, causing them to be higher-impedance than normal. There were also longer drain dimensions. All that just allowed the heat of conduction during ESD to be spread evenly, rather than superheat a small weakest-link somewhere and cause a permanent failure. A spark on the die would indicate that ESD-clamping had failed.
I'm sorry if my question appeared arrogant, especially from someone that knows nothing about microelectronics (me). I just wanted to be sure that I can jump into the P2 bandwagon. Normally I tend to stick to older technology.
Kind regards, Samuel Lourenço
Samuel, don't worry about a thing. If you are wondering about something, it's likely that other people are, as well. And I didn't register any arrogance, either.
In other process variations, voids are placed where contacts would normally be and serve as a means to arc from layer to layer and therefor can be constructed vertically. During the process another material is placed where the tungsten contacts would normally be, and then chemically stripped away leaving a void.
"In the ESD structures that you laid out, there was a lack of silicide implant in the big, multi-fingered ESD-clamp FET drains, causing them to be higher-impedance than normal. There were also longer drain dimensions." - We followed strict ESD guidelines from TSMC exactly, and even had the structures approved by OnSemi. I know for certain that silicide implant was in place. You and I even went over it with a fine toothed comb to verify that it was there. If there was any lack of material it was because the database was not streamed out correctly when moving to another process as a result of designing for one process and fabricating in another process. That's like following directions to make Cherry pie and expecting it to taste like Peach cobbler. It simply doesn't work.
I didn't know some processes made intentional voids. That's fascinating. I wonder if there are vacuums in them or trapped gases.
That ESD implant, if I recall, was actually a silicide block, and was laid out like a donut around the drain, so that silicide covered the drain contacts, but beyond that, the donut pattern formed a resistor to dissipate heat from ESD.
This is a side view, but looking down, MTOP would come to a sharp point(s) right at or just before the opening.
There is much difference in price between 180 nm and 90 nm?
90nm would be a little faster and might have more ram.
Could use an aid to finance " cross-funding".
I think if users Propeller, we could participate to help make a micro more efficiently and with better performance, would be willing to help.
10 $, 25 $, 50 $ * many users
Propeller microcontroller is a good, easy to use, it is worth betting on his brother PII.
I'm new to the forum, I thought it was reasonable to share idea.
I hope it's not a crazy idea.
A greeting.
That'll be a Prop3 question.
What you are talking about is crowd funding. Like Kickstarter for example. https://www.kickstarter.com/
Even at 50 dollars a head that might require 20,000 backers.
Given that PII development has been going on now for ten years they might be a bit hard to find.
I think it would be a bit of a non-starter.
90nm would probably cost $400k to tool up for, while 180nm is around $120k.
At this point, it would be a non-starter, but if we can get a lot of activity going on Prop2, there would be a very direct understanding of what people were getting involved in, with a 90nm, or maybe even 40nm, crowd-funded effort to make the same design run 4-6 times faster, but with huge RAM.
http://www.adestotech.com/news-detail/adesto-technologies-and-tpsco-announce-cbram-manufacturing-agreeme/
mentions using 45nm for their NV memory tech, with this qualifier
"The companies anticipate an approximate two-year ramp to bring up CBRAM technology in its new fab."
More than twice as 180nm. :surprise:
130nm, I think that is a more realistic alternative, remains an attractive increase in speed and memory. :thumb:
crowd funding, could be a help to Parallax?
Heater.
interesting.
https://www.kickstarter.com
For the Prop3 maybe. Chip's reply to Heater gave a possible Kickstarter path. Chip wants to demonstrate a finished product before asking for a ton of capitalisation money for what, I suspect, will have to be higher production volumes than Parallax is used too.