P2 Eval Board, support chips for better Test & Demo.
jmg
Posts: 15,173
With the P2 edging toward signoff, it is around time to look at Eval/Development Boards.
A quick look at what is out there in Board/Module land.
* Ardunio: old, 5V, and download and hope. Rather large in today's spectrum. OK as a second choice.
* Pi Zero : Not so much a MCU eval, as a New Form Factor Standard (Connector+PCB). Always 3V and smaller than Ardunio.
Vendors examples : All of these come with On-Board Debug & most have a user COM channel too.
http://www.atmel.com/tools/atsamd10-xmini.aspx
http://www.atmel.com/tools/mega328pb-xmini.aspx
http://www.silabs.com/products/mcu/Pages/DevelopmentTools.aspx
http://www.intel.com/content/www/us/en/embedded/products/quark/mcu/system-studio-getting-started-guide.html
http://hackaday.com/2016/03/31/intel-ups-the-dev-board-ante-with-the-quark-d2000/
http://www.nuvoton.com/hq/support/tool-and-software/development-tool-hardware/development-kit/?__locale=en
Some vendors use FS USB(12M) and some use HS USB(480M), and HS USB allows faster screen refresh on Code Step.
Common for HS-USB is FT232H/FT2232H, but I find another recent entry, that looks better on paper...
XR2280x Series Hi-Speed USB 2.0 Compound Devices
http://www.digikey.com/en/product-highlight/e/exar-corporation/xr2280x-series-hi-speed-usb-devices
These come in 0/1/2/4 UARTS and i2c and Parallel IO ( and you get Ethernet for free, not used for now... )
Similar price to FT232H/FT2232H, but XR2280x is rather smarter on all fronts.
Best match for P2 Eval I think is the 4 UART XR22804IL56-F ( 8mm QFN )
https://www.exar.com/content/document.ashx?id=21593
This has 4 x 15 MBd UARTs, so allows 1 Debug Channel, and 3 User UART channels, which can be RS485/9bit
P2 can support a large number of UARTS, so a means to Test/Demo those will be important.
You also get i2c, 100k,400k, (shame no 1M, 3.4M) & 32 parallel IO with a 60MHz SysCLK (shared with UARTs).
IO can also generate PWM, eg for checking P2 timing/capture & can configure for Hardware Flow Control (both RS485 and RTS/CTS).
Longer term, Parallax might be able to support a P2 as Eval-Link, but that will need a lot of software development, and will only ever be 12M USB
There are also Test/Demo advantages in not using the same device: You know you have an independent, 3rd party reference source, that is not likely to have a 'matching bug'.
Exar also look to have utils ready to test i2c and UARTs & GPIO
http://www.exar.com/common/content/document.ashx?id=21581
Suggested release & development :
Take the existing P8X32A Propeller QuickStart, & respin to XR22804IL56-F + Pi-Zero Form Factor (Connector+PCB)
( Probably do as two parallel layout designs, a P2 and a P1, with only the MCU cell area different. )
This gives quite useful P1 Test/Demo expansion, right now, and allows all the software flows to be tested.
i2c+ 4 x UART + 32 GPIO access, is going to be great for one-board Test/Demo of P1.
This also allows P1/P2 to appear as siblings, as the long term development resource is the same for both.
(Look at SiLabs EFM8/EFM32 for example of same SDK approach)
Addit: This is the GPIO Detail
EDGE - Enhanced Dedicated GPIO Entity
The XR22804 has 16 IO pins that may be assigned to the EDGE. By default, these pins are all assigned to the UART channel
A and channel B functions, either to the UART data and / or flow control pins or to the UART GPIO. Note that UART
GPIO and EDGE have separate register controls. Pins assigned to the UART function cannot be controlled by the EDGE
registers and vice versa.
The EDGE controller allows for GPIO signals to be individually set or cleared or to be grouped, such that the all pins in the
group can be simultaneously accessed for reads or writes. Note that on write accesses, output pins will change in 4-bit subgroups
on core clock (60 MHz) boundaries. For example, if an 8 bit data group is defined and the data value is written from
0x00 to 0xFF, 4 bits would change from ’0’ to ’1’ followed by the next 4 bits one clock cycle (~ 17 ns) later.
EDGE IOs can be configured as inputs or outputs. Outputs can be configured as push-pull or open drain and can be tristated.
Inputs can be configured to generate interrupts to the USB host on either negative or postive edge transitions.
Another feature of the EDGE controller is that up to 2 GPIO pins within the EDGE can be assigned to pulse width modulated
(PWM) outputs. Each of the PWM outputs can be used to generate an output clock or pulse of varying duty cycle.
Both low and high cycles can be configured in steps of 267 ns up to 1.092 ms. The output can be controlled to generate a
single "one-shot" pulse or to free run.
Hmm, wonder how that works as a Logic Analyzer ? - Seems a Logic Probe at least is in there, so 'activity LEDs' can emulate on PC screen ?
I make that PWM as useful for DUTY or Frequency generate for testing from 458Hz to 1.8726MHz.
Two of these are quite useful, for exercising all those smart pin modes, and this is all Crystal based timing, not USB jittered.
A fully self-contained Test/Demo example of pretty much every Smart-Pin mode should be possible
(well, minus USB ... )
They also look to have GUI to send 0x55 continually, on any UART, ( 300 bps thru15 Mbps) which gives more test coverage.
A quick look at what is out there in Board/Module land.
* Ardunio: old, 5V, and download and hope. Rather large in today's spectrum. OK as a second choice.
* Pi Zero : Not so much a MCU eval, as a New Form Factor Standard (Connector+PCB). Always 3V and smaller than Ardunio.
Vendors examples : All of these come with On-Board Debug & most have a user COM channel too.
http://www.atmel.com/tools/atsamd10-xmini.aspx
http://www.atmel.com/tools/mega328pb-xmini.aspx
http://www.silabs.com/products/mcu/Pages/DevelopmentTools.aspx
http://www.intel.com/content/www/us/en/embedded/products/quark/mcu/system-studio-getting-started-guide.html
http://hackaday.com/2016/03/31/intel-ups-the-dev-board-ante-with-the-quark-d2000/
http://www.nuvoton.com/hq/support/tool-and-software/development-tool-hardware/development-kit/?__locale=en
Some vendors use FS USB(12M) and some use HS USB(480M), and HS USB allows faster screen refresh on Code Step.
Common for HS-USB is FT232H/FT2232H, but I find another recent entry, that looks better on paper...
XR2280x Series Hi-Speed USB 2.0 Compound Devices
http://www.digikey.com/en/product-highlight/e/exar-corporation/xr2280x-series-hi-speed-usb-devices
These come in 0/1/2/4 UARTS and i2c and Parallel IO ( and you get Ethernet for free, not used for now... )
Similar price to FT232H/FT2232H, but XR2280x is rather smarter on all fronts.
Best match for P2 Eval I think is the 4 UART XR22804IL56-F ( 8mm QFN )
https://www.exar.com/content/document.ashx?id=21593
This has 4 x 15 MBd UARTs, so allows 1 Debug Channel, and 3 User UART channels, which can be RS485/9bit
P2 can support a large number of UARTS, so a means to Test/Demo those will be important.
You also get i2c, 100k,400k, (shame no 1M, 3.4M) & 32 parallel IO with a 60MHz SysCLK (shared with UARTs).
IO can also generate PWM, eg for checking P2 timing/capture & can configure for Hardware Flow Control (both RS485 and RTS/CTS).
Longer term, Parallax might be able to support a P2 as Eval-Link, but that will need a lot of software development, and will only ever be 12M USB
There are also Test/Demo advantages in not using the same device: You know you have an independent, 3rd party reference source, that is not likely to have a 'matching bug'.
Exar also look to have utils ready to test i2c and UARTs & GPIO
http://www.exar.com/common/content/document.ashx?id=21581
Suggested release & development :
Take the existing P8X32A Propeller QuickStart, & respin to XR22804IL56-F + Pi-Zero Form Factor (Connector+PCB)
( Probably do as two parallel layout designs, a P2 and a P1, with only the MCU cell area different. )
This gives quite useful P1 Test/Demo expansion, right now, and allows all the software flows to be tested.
i2c+ 4 x UART + 32 GPIO access, is going to be great for one-board Test/Demo of P1.
This also allows P1/P2 to appear as siblings, as the long term development resource is the same for both.
(Look at SiLabs EFM8/EFM32 for example of same SDK approach)
Addit: This is the GPIO Detail
EDGE - Enhanced Dedicated GPIO Entity
The XR22804 has 16 IO pins that may be assigned to the EDGE. By default, these pins are all assigned to the UART channel
A and channel B functions, either to the UART data and / or flow control pins or to the UART GPIO. Note that UART
GPIO and EDGE have separate register controls. Pins assigned to the UART function cannot be controlled by the EDGE
registers and vice versa.
The EDGE controller allows for GPIO signals to be individually set or cleared or to be grouped, such that the all pins in the
group can be simultaneously accessed for reads or writes. Note that on write accesses, output pins will change in 4-bit subgroups
on core clock (60 MHz) boundaries. For example, if an 8 bit data group is defined and the data value is written from
0x00 to 0xFF, 4 bits would change from ’0’ to ’1’ followed by the next 4 bits one clock cycle (~ 17 ns) later.
EDGE IOs can be configured as inputs or outputs. Outputs can be configured as push-pull or open drain and can be tristated.
Inputs can be configured to generate interrupts to the USB host on either negative or postive edge transitions.
Another feature of the EDGE controller is that up to 2 GPIO pins within the EDGE can be assigned to pulse width modulated
(PWM) outputs. Each of the PWM outputs can be used to generate an output clock or pulse of varying duty cycle.
Both low and high cycles can be configured in steps of 267 ns up to 1.092 ms. The output can be controlled to generate a
single "one-shot" pulse or to free run.
Hmm, wonder how that works as a Logic Analyzer ? - Seems a Logic Probe at least is in there, so 'activity LEDs' can emulate on PC screen ?
I make that PWM as useful for DUTY or Frequency generate for testing from 458Hz to 1.8726MHz.
Two of these are quite useful, for exercising all those smart pin modes, and this is all Crystal based timing, not USB jittered.
A fully self-contained Test/Demo example of pretty much every Smart-Pin mode should be possible
(well, minus USB ... )
They also look to have GUI to send 0x55 continually, on any UART, ( 300 bps thru15 Mbps) which gives more test coverage.
Comments
In terms of getting the P2 into the hands of serious developers... something like a P123-A9 board, with the same FPGA, but with the P1 replaced by a P2 seems to make sense. At other end, a P2 with external memory mounted onto a DIP chassis would make sense and would fit into the same case as the current Propeller Education Kit... maybe with an extra option for a battery management using more exciting batteries:) We need to know how to use the newer batteries safely... how better to learn?
The options and opportunities seem endless.
P123-A9 is seriously large and expensive, and is fine for Verilog testing, and meets that task right now.
Once P2 is available, why do I need an A9 ?
Maybe, but that is a niche target, and is not good for time-starved commercial customers, nor does it match the 'Works out of the box' Evals that others offer.
I would say someone will work up a DIP breakout, but the larger TQFP100 is not going to make that easy.
Perhaps SMD 0.1" headers on one side, and a glued P2 on the other, for 2 sided reflow ?
When? I want to know the exact day:)
And by the way, could you make a few dozen changes and make it so I can hook it up to an Intel Edison?... just kidding.
Glad to know you haven't shelved the idea... I think it is great.
- but at the price of an A9, who would want to do this ?
There are quite a lot of power supplies & decoupling and boot memory needed to bring up a FPGA, so that's not much different from the 1-2-3-A9 (or other A9 board).
I guess if someone wanted to field test a few A9.FPGA.P2 in as small as size as possible, they could likely get the Parallax PCB design and prune it down.
I can see more demand for BGA handling, with parts like MachXO3L-9400, (9x9xmm or 14x14mm) which could do a reasonable P1V, at a (sub $20 ?) price point.