Smartpin "Quadrature Encoder" mode returns erratic values
ozpropdev
Posts: 2,792
in Propeller 2
Chip
I been experiencing weird behaviour of the smartpins in quad. enc mode.
At first I thought it might be faulty encoders, so I replaced them.
The issue persisted so I have removed them and implemented fake ecoders in another cog.
The issue remained so I did a few tests and found that the issue seems to be related to the period between PINGETZ instructions.
in the included code the fake encoder cycles back and forth at low speed and displays the Z value spaced by its lower bits.
If the WAITX instruction @ main is enabled the following output is returned (Correct).
The results vary on each download.
The test code has been running on a P123-A9 board.
I been experiencing weird behaviour of the smartpins in quad. enc mode.
At first I thought it might be faulty encoders, so I replaced them.
The issue persisted so I have removed them and implemented fake ecoders in another cog.
The issue remained so I did a few tests and found that the issue seems to be related to the period between PINGETZ instructions.
in the included code the fake encoder cycles back and forth at low speed and displays the Z value spaced by its lower bits.
If the WAITX instruction @ main is enabled the following output is returned (Correct).
00001862 0000185A 00001856 0000184E 00001846 00001842 0000183A 00001832 0000182A 00001826 0000181E 00001816 00001812 0000181A 00001822 00001826 0000182E 00001836 0000183A 00001842 0000184A 00001852 00001856 0000185E 00001866When the WAITX @ main is removed erratic behaviour is observed.
00000000 0000023E 00000242 0000024A 00000252 00000000 0000025E 00000000 0000026E 00000272 0000027A 00000282 00000000 00000276 00000000 00000266 00000262 0000025A 00000252 00000000 00000246 00000000 00000236 00000232 0000022A
The results vary on each download.
The test code has been running on a P123-A9 board.
Comments
I'm looking into it right now.
You mean you checked the code in #1 and it ran 100% ?
Looking at the code, the delay patch seems to be in an unexpected place, (ie the loop has already taken many cycles sending data, why should a few more matter ? ), and it seems the counter itself is ok, just the read sometimes gets 00 by mistake.
The patch is right after a jump, could there be some interaction between pipeline and opcodes like pingetz ?
Is there enough timing margin in the FPGA's ?
OzPropdev: What range of delays is a fix, and does one or more NOP also fix ?
Addit: I also notice that failure seems periodic - it is always NYNYYYY ?
Could the loop time not be N*16 and so a variable phase on COG slot is occurring ?
( that would mean some NOPs could fix, and more NOPs could break again )
I fired up my DE2-115 board just as a point of reference.
Because the DE2 only has 8 snartpins and no smartpin on pin 62(Tx) I replaced the Tx code with a bit bang variant.
Code works fine with/without WAITX delay.
At first I thought this might be a Cyclone 4/5 timing difference.
Running the bit bang variant back on the A9 board and now everything works.
It seems to be a smartpin message issue from the async tx mode that upsets the quad mode smartpin?
The loop delay is likely also not exactly the same, so you could try inserting back dummy pingetz, and see if that
always breaks, no matter where it is inserted ?
I setup another smartpin in async mode but only ever reference it wuth a PINGETZ.
Works fine but does not (erratic quad. enc values), but a combination of the two works fine. ?????
I'm still thinking it's some sort of smartpin messaging issue.
One thing I did discover is that if I assign my dummy async Tx smartpin to a non existant smartpin the issue goes away.
So the code combination #2 now works on DE2-115.
Starts to look less like some marginal FPGA issue....
Maybe that just becomes a NOP ? - Chip will know how different a no-pin-there opcode is.
If you do 2 consecutive 'read encoder count' pingetz's, do they both have a failure pattern, or only the first one ?
I modified your test code slightly to display the encoder value on the A9's green leds.
By adding a async smartpin into the mix breaks your code too.
Particulary on rollover.
Edit: Same outcomes are observed using the three variants mentioned above.
As long as there is a Async PINGETZ before the ENC PINGETZ it works?
Ozpropdev, I got it to fail using your last program posted.
I see the problem. On the first clock of the GETPINZ instruction, it's reading the smart pin that was the object of the prior PINSETM/PINSETX/PINSETY/GETPINZ instruction. If that smart pin happens to be outputting a message header, the cog starts reeling in a message, starting on the next clock, from what is then the correct smart pin. So, it's sometimes using a wrong message header with the right pin, causing registration and sizing errors. Sorry about this. I should have thought this through better.
I'm fixing it now.
I'm sure glad you guys find things like this.
Jmg, you have the scariest imagination - a pipeline bug! There could be such things lurking, but, hopefully, we've weeded those out, already. Good guess, anyway.
Good if you have nailed it.
I'm starting up an A9 compile now.
It's nice when it's a quick fix.
The fix was maybe 10 minutes, but the compile takes 2 hours.
https://drive.google.com/file/d/0B9NbgkdrupkHby0xV0tsU3ZJZXM/view?usp=sharing
Any summary of what else changed ?
Dual-port LUT ? Better capture-mode controls ?
Dual-port LUT and phase setting in NCO mode. I'll document these things as soon as they are done and I'll make a new release.
Thanks Chip.
V8a running very nicely.
Cheers
Brian