Feasibility of making a 64 I/O + extra memory P1B?
Peter Jakacki
Posts: 10,193
in Propeller 1
I think I need to ask this question because I really need a P2 although all I really need is a P1 with more I/O and memory. Seeing we have P1V FPGA files I was thinking what would be the costs involved in producing a chip from these files? I have a design which will use 10k for the initial run just for that job and I'm thinking that maybe a run of 50k would be in order. So there would be the initial NRE and costs for each batch produced. Also which process would P1B use? Of course I'm talking about taking the big plunge here privately or as a group but would much prefer Parallax to run the show as I also would hate to make a product that competed against P1 while P2 languishes still in never never land, close, but always flitting about like Peter Pan.
Rather than go into too much detail perhaps Chip or some of the forum members could provide some guidance? Is it feasible to produce a P1B chip from P1V files and what initial costs would be involved? Am I insane? Perhaps but I need to know.
Rather than go into too much detail perhaps Chip or some of the forum members could provide some guidance? Is it feasible to produce a P1B chip from P1V files and what initial costs would be involved? Am I insane? Perhaps but I need to know.
Comments
You want 10 to 50K Propeller chips with extra memory and I/O. What is the maximum cost per chip that project can stand before it becomes untenable?
Let's say 10 dollars. So you have 500,000 dollars to spend on getting them made.
I reckon it's possible. I forget the figures that Andreas Olofsson mentioned when he was giving a presentation of chip design but that seems to be in the ball park for a relatively simple design.
Or it could perhaps be made in an ASIC for less: http://www.sigenics.com/custom-asic-cost-calculator/
It's a fascinating presentation anyway.
Anyone this thought about making a chip is probably too much trouble, I'm reexamining my other options now and may have to scrap what I've done so far and commit to an ARM for production.
Back in November of 2015 I started a thread about this in the P2 forum :http://forums.parallax.com/discussion/162721/about-p1-is-it-viable/p1
I took the initiative to get some preliminary discussions going among Parallax, Treehouse (the layout folks) and ONSemi, the fab house.
Progress has been slow, but we are not yet at a decision point to proceed or abandon the project. Although we have some price quotations at this time, some more cost analysis is required.
There are several features to be considered.... more HubRam will require a push from 350 to 180 nm technology, pushing up the NRE costs, but not horribly so.
Your potential application could be a serious driver in coming to a final decision to proceed. If you are interested, I would share via PM my list of needs/wishes to see if that fits for you.
Unfortunately this whole process still will take time as we do need some of Chip's time, but possibly not as much as getting the P2 to silicon..... I do not have much insight into that.
If you are interested, please send me a PM.
Cheers,
Peter (pjv)
LOL! I too think "P2" is way beyond "P1 version 2". To officially call it Propeller 2 now would be anticlimactic!
Yowzers! That sounds like a decision that you don't easily come back from! I hate to think of the number of non-vocal customers that are having the same thought...
The P1 does not cut it, the P2 does not exist, developing a chip is expensive and full of risk.
If you have to make a new Forth engine for whatever its is at least you know how to do that and have it under control.
If an ARM can do the task, then certainly, go that way.
For Tasks that ARM cannot do, P1V is more viable.
I see in another thread, reports P1V fits into a A3PN250 100 pin Flash FPGA 500 $9.81
That would seem to be a safer path, and commercially tolerable for many apps.
Probably many more than a few. Unfortunately, they're not left with much choice.
You could use a sub $1 MCU for security, alongside a P1, which would prevent slavish copy.
Or, a small FPGA/CPLD, if the problems are more at the hardware end of the scale.
Even the intel D2000, (250+ $2.53) could make an interesting co-processor, but it maybe a bit new for your time-lines ?
It does show stock, and the Eval is cheap, and it seems to have quite good maths and comms, but somewhat weaker on timing
How many COGs and how much on-chip RAM do you need? Are some of the tasks run in a COG something that could be done with much less custom logic? e.g. a UART? It seems like you're able to squeeze quite a lot out of a COG so perhaps you can find a low-end FPGA that would work. Any idea about your budget?
I just bought something a bit higher end to play with - one of those Terasic DE0-Nano-SoC boards for about $100. It has a dual core ARM Cortex A-9 running at 925 MHz (can run linux and has ethernet/USB OTG/UART to USB), and is an A4 (versus the A7 and A9 parts mentioned on the prop2 forums) so that's 40k logic elements in Altera terms, and has about 337 kbytes of internal memory. Your logic can use the HPS's SDRAM controller as well to access 1 GB of off-chip RAM.
If you do go back to the world of ARM where will you be posting about your forth ;-)
Certainly many FPGAs are in BGA, but if I sort the 18,000 odd FPGAs on Digikey for TQFP100, I get 713 that range from ~$5 to ~$25, and up to 46k bytes of memory.
100 pin is essentially the same PCB rules as tqfp64.
There would be a pin compatible upgrade path from P1+ to the P2.
Unfortunately, it seems the P2 has dragged on for so long now, and with the learning curve to the P2 instruction set, even without the smart pins, I wonder where the market will be and who will be left around ??? The forums are very quiet nowadays.
When P2HOT failed, almost everyone agreed that what we wanted was a P1+.
What we really need is a P1+ now, and P2 can follow a little later. I said that more than 2 years ago, and I still believe it today.
Certainly, Engineering is making what you want, from what you can get.
Then that dictate likely also excludes a P2 + Inner P1V, too large a die for that package.
There are few FPGA at 64 pins, but some smaller ones at 48QFN, that could do a P1V special, alongside a standard P1.
eg ICE5LP4K-SG48ITR-ND is ~$5 / 2k
The benefit of this, is you keep the software pool common, with some minor opcode extensions to make the P1V hum.
Downside is, two packages.
Or, if 64 pin is the real sweet spot, XMOS actually have 24 offerings there, so they may be a better short term target.
XUF208-256-TQ64-C10 claims 1MB Flash, 256K RAM, 42io, and 250 @ $7.69
That's all I've ever needed - a P1 with some more pins and memory. In fact, even the extra memory isn't really vital, because with more pins you could use an external parallel memory and still have useful pins left over.
Even 64 pins is not vital. 48 would be fine.
But I've kind of felt it was a bit presumptuous to tell a large corporation what chips to make. So I guess I quietly went off and built projects using a board that starts with A, because those boards became cheaper than the bare propeller chip.
Do how many cog and how much ram?
I seem to recall that we could get a P16X64 from the P1V FPGA, with 128K hub in the same FPGA footprint, after removing the resources that are not used by FORTH. If I recall these were video generators, ROM tables, unused assembler instructions. It might have had twice as much cog memory, but were were several configurations being tested.
It struck me that this was the low hanging fruit, as as there are very few unknowns, and the configuration seems to "just work".
Would P16X64-128(?) be useful for something besides forth?
This 100MHz (many instructions take just one cycle) NXP ARM M4 cost $2.54 at 100 units.
QFP100 with 66 gpio.
http://www.mouser.com/ProductDetail/NXP/MK22FN128VLL10/?qs=/ha2pyFadujOaTS62yr9HRld3UjVr6E6%2bk2XlKVudmqz5BxWVfv9QA==
If you want determinism (no IRQ on) could run some 50cent's M0 as coprocessor.
http://www.mouser.com/ProductDetail/NXP-Freescale/MKE04Z8VTG4/?qs=sGAEpiMZZMuoKKEcg8mMKDwQfRRt3jtqUSNXVxTrXek=
IAR Workbench support, free trial 32 Kbyte code size limitation.
https://www.iar.com/device-search/#!?devices_architecture=ARM&devices_vendor=NXP&tab=devices
GCC certainly enjoys CPUs with fewer instructions. I don't know exactly which instructions were removed, nor do I know which instructions GCC needs - but it sounds like something that would be very intriguing from that perspective.
Unfortunately, I do not have any commercial projects for such a chip.
@tonyp12: ARM is what I was using before I got caught up in Prop land. I've got boxes (literally) full of the latest dev boards as well and I used to use IAR workbench before but beyond the trial version it is very expensive. If only Parallax had what we wanted from the beginning, a P1 with more memory and I/O.......can't understand why one was never made ........ is Parallax at all concerned about this?
I guess the time to have done that was nearly two years ago when the P8X32A_emulation Verilog was released.
By the way. How come the P8X32A_emulation Verilog is not on the Parallax github? I could have sworn it was at some point.