Design Lock?
kbash
Posts: 117
in Propeller 2
Is the new chip layout stable to the point that would justify doing preliminary circuit board designs?
I bought Diptrace and took the time to design a board around Chips schematic for the "Hot" P2 a couple of years back when it looked like a release was only months away.
That didn't pan out of course. I don't mind revisions, they are a normal part of any design, but I've gotten to the point that I won't even tell my wife what I'm working on... she just rolls her eyes.
I'm not one of you "Superstars" out here doing the testing of the latest updates to the FPGA design ( I just barely understand most of the conversations... some, not at all!)
About the only thing I am reasonably good at is motion control and circuit board layout. My P1 boards have all worked great. Doing a board design is my own way of learning enough about a chip to be able to use it later.
The P2, offers a few more challenges to layout, but I figure if I can start working on it now... I might actually understand the chip well enough to do an acceptable job by the time hardware is actually available.
I'd like to contribute SOMETHING to the P2. Having a CNC control board ready to put chips on would offer only a small outlet for a few chips, but I'd like my time investment to be meaningful this time.
What's the consensus? Wait? Roll the dice again?
Any guidelines?
Ken B.
I bought Diptrace and took the time to design a board around Chips schematic for the "Hot" P2 a couple of years back when it looked like a release was only months away.
That didn't pan out of course. I don't mind revisions, they are a normal part of any design, but I've gotten to the point that I won't even tell my wife what I'm working on... she just rolls her eyes.
I'm not one of you "Superstars" out here doing the testing of the latest updates to the FPGA design ( I just barely understand most of the conversations... some, not at all!)
About the only thing I am reasonably good at is motion control and circuit board layout. My P1 boards have all worked great. Doing a board design is my own way of learning enough about a chip to be able to use it later.
The P2, offers a few more challenges to layout, but I figure if I can start working on it now... I might actually understand the chip well enough to do an acceptable job by the time hardware is actually available.
I'd like to contribute SOMETHING to the P2. Having a CNC control board ready to put chips on would offer only a small outlet for a few chips, but I'd like my time investment to be meaningful this time.
What's the consensus? Wait? Roll the dice again?
Any guidelines?
Ken B.
Comments
Here is the currently planned pin-out:
Those are the 3.3V power supply inputs for each set of four I/O pins. If you want good ADC quality, give a filtered 3.3V to one of those.
Oh, that makes sense. Very cool
Have any PCB trial layouts been done with this ?
I can see the mid-placement of VccIO gives the lowest theoretical paths inside the chip, but it forces traces into pairs, and adds vias, which may raise the system impedances, as well as increasing overall PCB area.
I think better for 2 or 4 layer PCB layout, is to reshuffle to have 4 signal pins, with alternating VccIO so you have this
P47
P46
P45
P44
VIO_44_47
VDD
VIO_40_43
P43
P42
P41
P40
Here, a single via is used per Byte of IO and the Vdd goes to an internal ring (PCB trace between centre PAD and Pins)
3 Caps can pack into 3 corners, for Vdd decoupling top side (more can go underneath), and the 4th corner is Xtal priority,
so Vdd cap there is slightly longer traces.
8 signal lines can cleanly route to byte wide devices placed nearby.
If I was doing this pinout, I would also push Static TESn to between 49 & 50, to give XTAL shielding from aggressor P31.
This leaves all I/O clean to the outside, and the space vacated outside the VIOs and Vdds could allow wider traces or even guard rings for them.
Love the Xi/Xo on the corner, and the placement of RESn on the opposite corner
It's nice to see comments about the PCB layout be a part of the design process. I suppose the "Big" guys do it as well, but there are a lot of us out here that probably won't contribute anything to the internal design of the P2, but might come up with something that makes sense about it's use out in the world.
jmg is right, a change of a pin or two could substantially improve ease of use and reliability. If it makes TREMENDOUS amounts of sense... we ( Chip ) should consider these ideas. However.... watching the "Hot" P2 grow in complexity day by day as "Just one more good idea" came into the picture should give all of use pause to think very carefully before making suggestions. Design creep has killed more than one of my own projects. I suspect that others of you out there have experienced the same.
The ONLY hardware idea I hope Parallax will consider ( and only after the P2 is a functional chip) is the the question of whether one of the cogs and a few of the smart pins might be chopped out and compiled into a small, 6-10 pin microcontroller suitable for embedded designs. Many of my P1 designs use just a single cog. I had to design a PIC into a recent consumer product because pennies were critical. Many consumer product designs are very un-glamorous, but a few thousand (un-glamorous) chips here and there might make sense for long term profitability for Parallax, particularly if the design is mostly complete anyway. ( I don't know enough about the way the chip design process works to even know if this is a valid idea or not. )
With that said... get the P2 done Chip, in any configuration, pinout or package that makes sense to you. We will deal with changes if necessary. ANY P2 done soon will be better than a PERFECT one in "Just a few more years. If you build it... we will come.
KB
Hi Chip,
I'm not sure if the Vdd pins without matching GND pins next to them would be the best idea, IMHO. That will make it difficult to AC decouple it. Are you relying on the ground pad alone for the ground and then one would use the caps on the back of the PCB for the decoupling? Also, won't that create noise issues on such an high speed design (I normally run from decoupling through vias)?
Don't take me wrong for the enquiring. I'm sure you've done your research, but I'm curious to why this design.
To add, one of the reasons I've liked the P1 pinout was that all power pins were complemented. By the way, you will be doing QFN, or also QFP?
Kind regards, Samuel Lourenço
Yes, all ground connections are through the thermal pad on the bottom of the package.
I know it doesn't look the most convenient for decoupling, but a few mm of trace and a via are still much lower impedance than the one mm of bond wire that's already on every pin.
I was wondering about two suggestions to increase the die space (to get 1MB of hub)
1. TQFP100 with 0.5mm pitch
2. TQFP144 with either 0.5mm or 0.4mm pitch
With a TQFP144 you would have 11 pins per side that could be used for gnd pins (connected to the ground centre pad). This would permit hobbyists to not solder the centre ground pad but still have ground connections via the pins.
Of course, the TQFP144 would increase the pcb are used quite a bit.
TQFP100 @ 0.4mm2 12x12mm/14x14mm(outside pins)
TQFP100 @ 0.5mm2 14x14mm/16x16mm
TQFP144 @ 0.4mm2 18x18mm/20x20mm (estimated as I didn't find 0.4mm specs)
TQFP144 @ 0.5mm2 20x20mm/22x22mm
TQFP144 is quite common. Not sure about something between 100 & 144 pin QFP packages.
That memory alone, can be larger than single chip MCUs, and similar in price.
A two package solution, is not going to play well in your 'consumer product where pennies are critical' area.
There are other companies already serving the 6-10-16 pins and 3mm or 4mm package and if you search at Digikey, you find just over 30c in modest volumes gets ADC/UART/SPI/i2c Code in Flash and In Circuit DEBUG, in a 3mm package.
You can even get 64KF and 4KR in a 3mm QFN package, for a low price.
I believe on the die, there are matching GND pins next to them, as well as some on-die capacitance.
Those GND pins bond down to the thermal PAD.
For the most aggressive decoupling, yes, you would place caps underneath, and probably use 4+ layers.
There is a reasonable gap between Thermal PAD and Pads on the PCB.
Some designs use via-in-PAD, where they want shortest possible connection to the ground plane capacitance.
This also allows smaller, tighter designs.
The P2 will likely never be able to compete on price alone. And it will be worse at the low end.
However, for less work, the P1 & P2 find niches where they excell in features and development and base cost is not a problem.
For example Test and measurement and instrumentation designers may be forced to currently use a FPGA to augment their MCU of choice, and the P2 will compete with FPGA on price, where someone needs "smart memory", and/or the Smart Pin Cells.
If you need memory, FPGAs get costly very quickly.
Any chance that there will be more hobbyist friendly packages for the P2? I mean, with a bigger pitch? On the positive side, QFPs are always much better to solder than QFN's. For instance, I had to use the QFN version of the FT230X, that has a pitch of 0.5mm, and even using stencils to reflow solder those, I never got one right. There are always some pins requiring rework.
Other package good for the P2 would be a PLCC-100 (with less Vdd pins and more GND pins - pins would have to be rearranged indeed). I know that the package is "ancient" by "modern" standards, but is can be used on a socket and would be the equivalent of the DIP-40 for the P1.
Kind regards, Samuel Lourenço
I believe it was previously mentioned that the chip would initially be available in one package, and that would seem to still make economic sense.
To support hobbyist market, you can expect Parallax and/or third parties will make breakout boards available.
Questions like this can only be answered more finally once the product is actual, but you should have great confidence that options will be available when the time comes!
I see. However, I also thought of a bigger pitch package for industrial applications. Those are preferred for the heavy use (and abuse) and harsh/corrosive environmental conditions on an industrial setup.
It makes sense on an initial stage to make the P2 available in one package.
Kind regards, Samuel Lourenço
We even re-did a PCB design recently, because the higher performance PLCC-44 socket we were using, pushed up in price and became harder to get. If even PLCC-44 is thinning out, PLCC-100 is long dead, and better done as a module.
Perhaps. There may be a market there, could be looked at in 2017 ?
Note those users avoid sockets if at all possible, so your plcc-100 is out there.
I have seen a move for Asian vendors to offer two pitch choices, especially around 64 pins, where 0.4/0.5 and also 0.8 are offered.
Not sure if those have a GND tab, will look for that next time.
I think that 0.8mm is driven by wave soldering - checking with Infineon, I can see they mention a 0.8mm at 44,64,80,128 package, but 100 pin is only offered in 0.5 and 0.65
I first started using PLCC-68 in a design 26 years ago. Pretty sure they have been around longer than that.
My fav would be a QFP with underside thermal pad. This has the advantages of cheap surface mount but still reworkable and has a little structural give.
??
I think the P2 is QFP with thermal PAD, not QFN.
That's right.
Anyway, here is a screen shot of the P2 footprint that I did alongside the 80-pin MEC connector from the CVA9. There's also an incomplete P2 prototyping adaptor as well.