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Prop IO Pin Voltage Drop vs. Current — Parallax Forums

Prop IO Pin Voltage Drop vs. Current

Hey guys,

I've taken some measurements of the nominal open circuit voltage on my prop io pins, and its around 3.2v when high - the voltage drops down to about 2.6 @ around 25mA. Does anyone have any experimentally acquired measurements for v vs i?

Comments

  • Data sheet under DC Characteristics states:
    Voh     Output High Voltage    Ioh = 10 mA, Vdd = 3.3 V     2.85 V (min.)
    
    So it looks like your 0.6 V drop at 25mA is probably within specs.
  • Open circuit voltage should be the same as Vdd so you should check that too, and your meter!

    ALL circuits have some resistance or voltage drop in their outputs, only poor simulators would deliver 10A for instance with zero voltage drop. With the CMOS outputs on the Prop I think the ÖN resistance is around 45 ohms. If you drive an LED or a BJT transistor then the voltage it drops down to doesn't really matter, only the current. When you drive MOSFETs then the voltage matters but in that case they do not draw any static current.
    So .... NO PROBLEMS.
  • Vega256Vega256 Posts: 197
    edited 2016-03-10 22:23
    Open circuit voltage should be the same as Vdd so you should check that too, and your meter!

    That's what I thought, but I dismissed it as a small amount being lost somewhere from within the chip.
  • measure between Vdd and the I/O however there should be no "lost" voltage into an open circuit although I am assuming you are using a decent DMM.
  • measure between Vdd and the I/O however there should be no "lost" voltage into an open circuit although I am assuming you are using a decent DMM.

    It's because Vdd isn't 3.3V; it's 3.21V, and Voh is 3.19V to be more precise.
  • Vega256Vega256 Posts: 197
    edited 2016-03-11 00:36
    ...With the CMOS outputs on the Prop I think the ÖN resistance is around 45 ohms...

    So can I use 45 ohms for future calculations? I'm guessing this is an approximation since we're talking about non-ohmic CMOS outputs?
  • Peter JakackiPeter Jakacki Posts: 10,193
    edited 2016-03-11 01:23
    if though you measured from vdd to i/o with even a poor meter it should read zero volts drop into an open circuit. Conclusion therefore is that your meter is loading up the I/O. MOSFET conduction is ohmic so use this Ron figure as a guide
  • Vega256Vega256 Posts: 197
    edited 2016-03-11 01:55
    if though you measured from vdd to i/o with even a poor meter it should read zero volts drop into an open circuit. Conclusion therefore is that your meter is loading up the I/O.

    Yep. I'm getting a 20mV drop from vdd to io. It's past due time that me and this radioshack mm part ways.
  • i think you must have something loading on that pin, 20mV indicates around 400ua or about 7.5k load, so it's not open-circuit from what i can tell.
  • Vega256Vega256 Posts: 197
    edited 2016-03-11 02:01
    Nothing on the pin. Should other pins and their connections affect the resistance? If it is the case, well then nevermind; I have a bunch of other stuff connected.
  • TubularTubular Posts: 4,702
    edited 2016-03-11 11:36
    Here are some curves I measured a while back. If you want a figure of merit, go with 28 ohms for a 3v3 system

    http://forums.parallax.com/discussion/135845/p8x32a-pin-driving-fet-resistance-graph

    Regarding the VDD drop you also have the impedance of the vdd connection net, which could explain the ~20mv drop depending on how many active cogs you're running. Furthermore this might be slightly worse for DIP vs QFP/QFN, since there are fewer power connections. There was some mention of double bonding those incoming supply rail ties, but I presume this applies both to DIP and QFP/QFN
  • jmgjmg Posts: 15,173
    Vega256 wrote: »
    So can I use 45 ohms for future calculations? I'm guessing this is an approximation since we're talking about non-ohmic CMOS outputs?

    Taking the numbers above

    (3.3-2.85)/10m = 45 Ohms (worst case)

    (3.2-2.6)/25m = 24 Ohms (your measurement aka typical)

    Worst case specs cover corner silicon, and highest T and lowest Vcc, so it is common for typicals to be around half of that (as we see here)

    When dropping under one third of supply, (as here) CMOS pins are broadly resistive.
  • Vega256 wrote: »
    Nothing on the pin. Should other pins and their connections affect the resistance? If it is the case, well then nevermind; I have a bunch of other stuff connected.

    No, the resistance is the channel resistance of the output FET on the pin. Yes, it is very resistive (if you don't overload
    the pin), its just Rds(on) of a PFET.
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