VGA 800x600 4bpp driver with text & graphics support + XGA 1024x768 4bpp
ozpropdev
Posts: 2,793
Hi All
Here's a VGA driver for 800x600 @72Hz with 16 color palette.
Text uses the Prop1 16x32 font and supports foreground & background color.
Rotated text mode is also supported (90 degrees left).
Basic graphics support of plot line, circle and rectangle is included.
Plot text string, hex string and decimal signed and unsigned string too.
Demo code attached.
Version 7 here - More modes and improved performance
Here's a VGA driver for 800x600 @72Hz with 16 color palette.
Text uses the Prop1 16x32 font and supports foreground & background color.
Rotated text mode is also supported (90 degrees left).
Basic graphics support of plot line, circle and rectangle is included.
Plot text string, hex string and decimal signed and unsigned string too.
Demo code attached.
Version 7 here - More modes and improved performance
Comments
Sweet, when I fire up my P2 I will try this out.
Look forward to doing stuff with this.
Or... external capture with a gaming capture device
Would need adjustments to work with this resolution and bpp though...
@ospropdev: Looks great! Nice work man.
(goes back to project, tries to avoid shiny things...)
I was running it @ 3M baud with mixed success.
I switched over to a Ft2232H and pushed up to 8M baud with instant stability!
If we had fractional bit rate control maybe 12M baud might be within reach. Looks encouraging.
That's pretty impressive
Yes, & fractional support would be nice.
I think the HW needed for USB, where the Baud-NCO-adder resets on edges, can give fractional baud 'for free'.**
I've found FT232H/2232H are ok here at 12MBd PC-Tx only, but in loop-back my system tests drop some chars at 12MBd, ok at 8MBd
** With USB on every 2nd pin, that does raise a detail question over BAUD control (which can be on all pins).
I guess simplest is to have that Baud-NCO-adder reset on edge available on all Baud generators ?
Intermittently @ 3M it drops a block of data, works fine @ 2M though.
I haven't seen the same behaviour with the Ft2232H, no dropped data @8M.
One experiment I might try is using both channels of the Ft2232H and splitting the
data into 2 chunks. Dual Tx @8M would be interesting if it works!
Sounds a good test.
There is also a Fast Serial mode (Clocked Async) in FT2232H, that can test faster :
FSCLK Driven by P2, allowed up to 50MHz in specs.
P2 polls FSCTS, and sends a byte when High (FSCTS pulses low for each byte in)
Diagrams show FSCLK as continuous, and it samples an Async-framed FSDI on the rising edge. (FSDI cannot change on that edge)
80M/4 clock & slower should be comfortable, with maybe 80M/3 and 80M/2 possible.
This would require the CLK and TxD overflows stay in sync, once started, and that Tx is always paced from Baud-rate.
I think PC-> P2 at 80M/2 may not be supported, even tho it is a Sync signal ?
Chip has said before Async limit is SysCLK/3, but maybe SysCLK/2 can work with a CLK signal (Still Async, not Sync, but no sampling issues )
It also claims 12MBaud, but using HID class. Pricing is sharp at ~$1.53 in 100 off qtys, significantly cheaper than FT231X, and QFN package is 5x5mm
Could make for a nice high speed prop plug revision
I was able to split the pixel data and send it via two serial channels @ 8M baud.
Here the code snippet of the TX code. Getting a big chunk of data into the PC that fast is great but is limited by how fast the PC can deal with it.
Has some interesting application though.
The issue is I can't get the data out of hub quick enough to feed the FT2232H.
For example the expected "best case" for a 120k block @8M baud should be 150mS.
The best I can do with tight code is 198mS.
Of course the real silicon will improve these figures.
Still good though.
Edit: BTW The code above takes 264mS to blast 240k out.
Can you do a RDFAST, then RFBYTE instructions for getting the data out? You'd have to interleave it afterwards on the PC side.
The FT2232H allows this mode ONLY on the first channel. The FT232H only has one channel and also supports this fast mode.
When the FTDI is configured in this mode it sources a 60 MHz clock and transfer 8 bits per clock.
I am waiting for the P2 documentation about the serial SYNC modes. I want to use two UM232H modules to transfer data between P2/FPGA and computer using two USB channels.
If dual 8MBd is showing signs of saturation, 4 bytes at once would help.
If doing that, you should look at FTDI mode of FAST SERIAL mode too. Gives50MBd.
I THINK P2 can mostly do that now?
Needs up to 50MHz clk continuously from P2, and there is a FSCTS handshake line.
Data is ASYNC framed, start bit = L
There is a optional 9th bit to signal channel- that could complicate 32b blocks?
TX needs to stay phase locked with clk, even with FSCTS and multi bytes & pauses.
RX support to Sysclk /2 is needed (no phase jitter can occur, as P2 generates the CLK.
The FT600 has a similar FIFO mode, ftdi generates clk.
Choices are 16 & 32 wide.
The streamer should manage the data rates, but could need some handshake support.
4b : manages the main-bandwidth side of QuadSPI
2b : There is a Dual-SPI, which could also cover JTAG (needs 1b Rx), and I'm not sure if x1 is already in streamer modes ?
1b : Is a useful way to send the address/command fields for many QuadSPI parts, which lack a Sticky-Quad mode.
Some flash parts can be set to take address in Quad, but the SRAMs out there now, seem to have 1 bit link for the address/command, then they flip to Quad IO.
With the above, JTAG uses 2b Streamer out, for encode of TMS and TDO, and TDI is 1b streamer in.
User preloads the data and selects N clocks.
QuadSPI RAM use 1b out for Address.Command, then flip modes ? to 4b IO
2x QuadSPI, could use 2 streamers, but they need to be in-sync ?
Addit:
Checking SRAM :
Microchip have a Sticky-mode on their 20MHz QuadSPI RAM, needs one byte sent to set, and stays in Quad until reset. One set, Commands and Address are sent Quad.
VLSI have faster 36MHz QuadSPI RAM, but that needs 32 clocks in 1b to send command/address, then it flips to Quad for that packet.
Oops, something is wrong (just looked at actual output).
There is a difference between format of Windows BMP color entries and P2 palette entries.
Windows BMP has alpha byte on MSByte and P2 has zero on LSByte.
So, I think I need to lie or cheat by one byte to make it work right...
Can't just offset the hub reading by one byte? Guess it would need a non zero alpha too