Sanity checking the USB design with OpenCores.org.

LewisD

First, I am not qualified to evaluate verilog code or USB designs.

But I thought Chip could compare what he has to what is in some of these open cores to see if it has all of the bits and LUTs it needs. (http://opencores.org)

This one says 111 LUTs, That seem similar to what he is at now.

http://opencores.org/project,usb_phy

They have several to look at…

http://opencores.org/project,usbhostslave


I am a LONG time lurker. I finale got off my duff and reset my password...

cgracey

Thanks, LewisD.

I will look at those.

Just today, things finally congealed in my head regarding what is needed and how you'd present it to the interface that software will use. Some of these detours are really taxing and I feel like I'm back at square one, rather than almost done with this chip.

USB 1.1 is kind of neat, really, but the business dimension of it is quite unpleasant.

tonyp12

Are we only going for 12mbs and not 480 Mbit/s highspeed 2.0?

Here is some usb2.0 info, some parts will be done in cog software probably
http://esatjournals.net/ijret/2012v01/i03/IJRET20120103016.pdf
http://www.eetimes.com/document.asp?doc_id=1279155

http://www.slscorp.com/ip-cores/communication/usb-20-device/usb20sr.html?page=shop.product_details&product_id=52&flypage=flypage.tpl&pop=0