The other question is can I confirm what the pinout will be for the BeMicro A9 board so I can incorporate this footprint into my main board. I've decided that I will connect VGA and a keyboard (maybe LogiTech via nRF24L01) and make this a standalone system as it will be fully loaded with Ethernet, dual SD cards, four RS485 buses, Bluetooth and whatever else I can think of etc. This A9 board footprint would ideally be connected up to a real P2 footprint as well.
EDIT: This board or a slightly different form could be made available to P2 developers who need an embeddable industrial rated control pcb for early products.
Specs: P2FPGA+P2 footprint, SDx2, Serial Flash, DS3231 RTC, VGA, W5500 Ethernet, ESP8266, 7-24V SMPS, RS485x4, nRF24L01, USB/PS2 socket, audio out, serial/USB etc
Apparently I can buy the MEC R/A edge connector for this board too, even easier.
P2 pinout I think you need to look in older posts, where the package and pin were nailed down.
Of course, late changes are always possible, but Chip may know if the Custom PAD Ring design is completed to enough to lock-in one package.
FWIR, there were not a lot of choices of package anyway, around exposed PAD 100pin, largest die cavity.
I found this from Chip, I think is latest-thinking ?
100 pin 14x14mm exposed thermal pad TQFP package (Tja=20) with internal down-bonds to GND, so no pins needed for GND
16 x 1.8V VDD pins, at four per side, with internal down-bonds for GND
XI, XO, RESn, BOEn pins
64 I/O pins with a unique 3.3V VDD pin for every 4 pins (and internal down-bond for GND) - this is important for analog and high-speed switching
(that makes 100 pins, not including 32 internal down-bonds for GND)
J4 isn't much use, just a few sparse LVDS pairs.
J1 is vaguely DE0-Nano Compatible,
Rogloh used the 80 pin connector for his P1V max10 design. From memory it offers around 50 gpio. I think its probably the way to go, frankly.
I have a few of those samtec connectors I can send up, if you get stuck.
That's good to know as I plan on using those connectors as I can also get them easily from Newark or Bristol etc. So has soon as I know what's what I can incorporate that into my PCB which at the moment also has a couple of less ideal P1s as backup. I may get up to 10 CV-A9s at present but I'm tempted to buy all 149 almost (if they would let me).
Long term you should be fine. As I recall, Chip said he would be releasing the sources when the P2 is in the books. It took me a while to be able to make even the most minimal changes to the P1 and that took a lot of help. But when the sources are available, changing the pin assignments should be straight forward. At that point, the FPGA fun won't be so much in changing the design but adding stuff around it. The nice thing about Chip supporting some of the other platforms is that there will be designs made for other platforms, which can be brought onto the A9 and still leave plenty of room to play. Chip is about to max out the A9 with the full design... so having some more limited designs is really a God-send. There is about enough room left for a couple XORs and NOT2s:)
J4 isn't much use, just a few sparse LVDS pairs.
J1 is vaguely DE0-Nano Compatible,
Rogloh used the 80 pin connector for his P1V max10 design. From memory it offers around 50 gpio. I think its probably the way to go, frankly.
I have a few of those samtec connectors I can send up, if you get stuck.
That's good to know as I plan on using those connectors as I can also get them easily from Newark or Bristol etc. So has soon as I know what's what I can incorporate that into my PCB which at the moment also has a couple of less ideal P1s as backup. I may get up to 10 CV-A9s at present but I'm tempted to buy all 149 almost (if they would let me).
115 left in stock, $171.00 tax and shipping to me, oh the things I do for P2 and Tachyon
I used a 10.3mm pad and also tied the Amkor details with the one from ON Semi as well. So it's a 0.5mm lead pitch, the leads add an extra 1mm per side and my landings takes into account hand soldering/rework by having that little bit extra extending out. Of course once this package is soldered down with the big central pad then it won't be that easy to get off again.
I used a 10.3mm pad and also tied the Amkor details with the one from ON Semi as well. So it's a 0.5mm lead pitch, the leads add an extra 1mm per side and my landings takes into account hand soldering/rework by having that little bit extra extending out. Of course once this package is soldered down with the big central pad then it won't be that easy to get off again.
Hand soldering would normally only be touch up in case of bridges etc and the longer pads make that easier. All my smd work is done with paste and toaster oven so it will solder up easily enough. It might still be possible to hand solder the device by means of vias from behind after pasting the pad which I might do if I think some didn't reflow properly.
I used a 10.3mm pad and also tied the Amkor details with the one from ON Semi as well. So it's a 0.5mm lead pitch, the leads add an extra 1mm per side and my landings takes into account hand soldering/rework by having that little bit extra extending out. Of course once this package is soldered down with the big central pad then it won't be that easy to get off again.
How do you hand-solder the central pad?
I'd design the PCB with a ~4mm plated hole under the chip. Use partitions on the solder mask to disallow solder in that area. Then, you could reflow it OR hand solder it.
Comments
So it looks like the BeMicro A9 will be on Chip's list then as I am definitely going ahead with incorporating this footprint into my main control pcb.
Some have mentioned that the pinout for P2 is "set", but is that so and where is the latest information?
Not good. Wishing you a speedy recovery.
EDIT: This board or a slightly different form could be made available to P2 developers who need an embeddable industrial rated control pcb for early products.
Specs: P2FPGA+P2 footprint, SDx2, Serial Flash, DS3231 RTC, VGA, W5500 Ethernet, ESP8266, 7-24V SMPS, RS485x4, nRF24L01, USB/PS2 socket, audio out, serial/USB etc
Apparently I can buy the MEC R/A edge connector for this board too, even easier.
I recall some pin out info went past...
Here it is:
http://forums.parallax.com/discussion/161974/first-look-at-the-bemicro-cv-a9-fpga-board
P2 pinout I think you need to look in older posts, where the package and pin were nailed down.
Of course, late changes are always possible, but Chip may know if the Custom PAD Ring design is completed to enough to lock-in one package.
FWIR, there were not a lot of choices of package anyway, around exposed PAD 100pin, largest die cavity.
I found this from Chip, I think is latest-thinking ?
100 pin 14x14mm exposed thermal pad TQFP package (Tja=20) with internal down-bonds to GND, so no pins needed for GND
16 x 1.8V VDD pins, at four per side, with internal down-bonds for GND
XI, XO, RESn, BOEn pins
64 I/O pins with a unique 3.3V VDD pin for every 4 pins (and internal down-bond for GND) - this is important for analog and high-speed switching
(that makes 100 pins, not including 32 internal down-bonds for GND)
J1 is vaguely DE0-Nano Compatible,
Rogloh used the 80 pin connector for his P1V max10 design. From memory it offers around 50 gpio. I think its probably the way to go, frankly.
I have a few of those samtec connectors I can send up, if you get stuck.
That's good to know as I plan on using those connectors as I can also get them easily from Newark or Bristol etc. So has soon as I know what's what I can incorporate that into my PCB which at the moment also has a couple of less ideal P1s as backup. I may get up to 10 CV-A9s at present but I'm tempted to buy all 149 almost
Long term you should be fine. As I recall, Chip said he would be releasing the sources when the P2 is in the books. It took me a while to be able to make even the most minimal changes to the P1 and that took a lot of help. But when the sources are available, changing the pin assignments should be straight forward. At that point, the FPGA fun won't be so much in changing the design but adding stuff around it. The nice thing about Chip supporting some of the other platforms is that there will be designs made for other platforms, which can be brought onto the A9 and still leave plenty of room to play. Chip is about to max out the A9 with the full design... so having some more limited designs is really a God-send. There is about enough room left for a couple XORs and NOT2s:)
regards
115 left in stock, $171.00 tax and shipping to me, oh the things I do for P2 and Tachyon
Here is the final planned Prop2 pinout:
As far as the A9 board pinout goes, that can be whatever you want.
If that is the case then it is similar to this with the QFP44 P1 inserted for reference.
That's right. The body is 14mm x 14mm. There's a big exposed GND pad on the bottom. All GND connections from the die are bonded down to that pad.
so VSS is the thermal Ground pad as I understand it.
I get it know.
I think Vdd is the core voltage (1.8V ?) and VIO is the I/O pin voltage (3.3V ?).
That's right.
For each VDD and VIO, there is an adjacent GND down-bond to the thermal pad, for a total of 32. This saves a lot of pins.
Should be, with a VccIO pin for every 4 IO pins, that's a lot of choices.
( & some routing challenges, with all those supply pins)
What size is the big exposed GND pad ?
The die pad is 10.7mm square. I'm quite sure that would be the bottom dimension, too.
+Bonding allowance ?
Is there a package vendor part number chosen ?
They usually have drawings, showing the actual PCB plane exposed part of the paddle.
eg here I find 10.3mm PAD for Amkor TQFP100EP
http://www.amkor.com/go/epad_lqfp_tqfp
It's for built-in scan test, to verify all logic and flops.
I'd design the PCB with a ~4mm plated hole under the chip. Use partitions on the solder mask to disallow solder in that area. Then, you could reflow it OR hand solder it.