Smartpin Quadrature encoder example
ozpropdev
Posts: 2,792
in Propeller 2
Here's a demo of the smartpin quadrature encoder mode.
Totalizer value is displayed on the 16 leds of the P123-A9 board.
'Quadrature encoder demo - P123-A9 on P0/P1
dat org
or dirb,##$ffff 'enable leds
pinsetm mode,#0 'setup smartpin
pinsetx #0,#0 'set x parameter
or dira,#1 'enable smartpin
.loop pingetz adra,#0 'get totalizer value
mov outb,adra 'send to leds
jmp #.loop
mode long %1_10_10000_0001_0000_00_0_0000000000000
'
{
MMMMM = 10000 = A/B-input quadrature encoder counter
X[31:0] establishes a measurement period in clock cycles.
If 0 is used, the count operation will not be periodic, but continuous, like a totalizer.
Quadrature steps are counted through the measurement period, then the result is placed in Z, IN is raised, and the process repeats.
D/# = %1_DD_MMMMM_BBBB_AAAA_LL_T_PPPPPPPPPPPPP
BBBB = x001 = relative +1 pin’s read state
AAAA = x000 = this pin’s read state (default)
DD = 10 = output enable off
}
Multiple encoders handled in a single cog will be a breeze.
Comments
Cool, Looks simple enough
31 Encoders anyone ?
Given the Selector-Reach feature, it should be possible to Generate a test case on 2 OUTPUT pin, and connect Quad to that, to check readback.
Then, the dual-connect feature can extract period and Counts, with 2 reads. - all on just 2 pins.
eg Test Period of ~127 SysCLKs and a slower read-difference loop of maybe 24384 SysClks should display 11000000 on Quad-Diff and 01111111 on Period capture.
It would work, but it's fun to play with pushbuttons and manipulate the total. It's instructive.
Well, yes, but ozpropdev already had Quad counting working with an encoder, and I'm thinking about Smart Pin Test Coverage.
To me, self test is simple, as it is highly portable and can duplicate on other systems.
The test code does not change with buttons vs a real encoder.
What is the theoretical upper Clock limit in Quad Mode ?
(edges per second) ?
What happens above that ?
It will track an edge per clock.
On every clock, A and B and their prior states are considered, in order to inc or dec the counter.
So, at 80MHz it could track up to 80M edges per second. You would probably want to not feed it more than 40M edges per second, though, to be safe. If you exceed the edge-per-clock limit, it would skip.
To self test this at every clock, P2 could generate two /4 Period signals, (20MHz) shifted 90' & connect 2 Quad pins to that ?
Which modes can do that Generate ? NCO, with different preload phase ?
The idea of Spin2 being able to tap into these marvellous features perhaps with a single macro like instruction.
i.e QUADENC(20,21,V1) ' for quad encoder input on pins 20,21
Then from there any reference to V1 simply is a PINGETZ V1,#20
- I think up to 32 NCOs could then be preloaded and launched this way ? - more with a small correction on two launch points.
Yes and yes. It saves loading X and Y with special 32-bit constants.
What would be good for initiating a servo motor or a stepper? How can we improve the design?
Brian,
I actually cnc'd my own encoders a while back... and it is a good thing, because it now
allows me to remember what is going on and I can worry about Chip's wonderful manifestations.
Andy's diagrams, your example and this discussion really helps. I just went through the documentation again and I still need to see an example as Chip mentions for using phase. I was assuming that we would watch with a waitedge ... but then that doesn't seem to make any sense:)
Thanks again to jmg.
Rich
Servo is DC based, so the PWM would cover that.
Q: Does the dithering feature discussed, have the ability to apply to a PWM LSB ? **
- ie allow higher frequency PWM switching, with a lower-period average. Motor inertia smooths to the average.
Stepper is along the lines of test-modes for Quad Encoder.
Something like a NCO feeding a Quadrature Pair, with Up/Down (or left/right) control for direction.
That might be a good example for State Modes (unless another mode can do this ?)
Can State do NCO Clocked, 2 bit Gray Counter U/D ?
This could also connect to a Quad-Counter, to feed-back actual position.
Gets close to Stepper-Servo like operation in the pins
Feed in Speed and Direction, and get back nett position.
How many pin cells are needed here ? 2? ( or 3?)
(Speed is known, so just one Quad Counter is needed)
** Addit: Seems like much of the Dither logic is already there in DAC modes, just need mapping to PWM.LSB rather than DAC.LSB ?
Q: Should dither be Compare Based, or Rate Multiplier Based ?
Oh, I interpreted this to be a reference to no mention of the Index signal (aka: Marker Pulse) which is typically gated with the CHA and CHB to establish a zero point. The ability to compare this once/rev pulse with the encoder count is useful for checking count integrity, also.
It seems that pretty much every dedicated quad-decode device on the market features digital noise filtering. The following is a quote from a MC document:
That is quite a lot of logic you have added.
The Pins are best doing bit-level stuff, especially those operations that need to be fast.
Word-level slower operations, can be done in software.
That said, Chip does say there are single bit FLAGS available in each mode. "to indicate when the smart pin has completed some function"
With the Multiple-attach feature, you can allocate more than one Pin-Cell to the Quad Pins.
Attach-2 is natural (no pin cost), and I think Attach-6 is the limit.(but that has a pin cost)
Position and Period(velocity) are already suggested as one pair of attach.
What you describe, may be possible with
Position (absolute) and Position(relative) where the counter sign (MSB) is mapped to Flag.
In operation user preloads the distance to travel, and the signal flag changes when the relative counter gets to zero.
This could allow lower power or lower MHz operation, than fast Full Value polling of a number of Quad channels.
I read that PDF about the digital noise filtering and it was very useful. I've come to the conclusion that this would be best addressed by having a general filter in place for the A and B inputs on every smart pin. This would add minimal logic, but serve every mode. I just need to find a nice way to implement it via the PINSETx instructions. It's really good you brought this up.
Some optional filtering is nice to offer, as there are pluses and minuses.
Quadrature counters already have natural filtering, you just need to ensure the narrowest fed pulse is still legal.
I think that is there already ?
On Capture or Count type signals, additional filtering can be beneficial, as no filtering at all can capture very narrow glitches, if they occur right on the clock edge,
That is certainly best avoided.
The down side is, each filter stage vote you add, extends the glitch width, but also lowers the maximum frequency.
It is common for MCUs to run PLLs at least 2x the SysCLK, as that guarantees 50% duty cycles and so improves timing margins.
I like the idea of feeding that 2x SysCLK into the Filter FF's so you still have the vote benefit, but can have less impact on maximum frequencies.
I've also seen small Async prescalers provided, at the pins, which allows higher than SysCLK pin toggle, but can still feed a filter with Sub-SysCLK limits.
This compromise works, because usually if you have high MHz signals that push SysCLK, you do not mind measuring over some multiple of cycles.
000 = no filtering
001 = divide by 1 filtering
010 = divide by 4 filtering
011 = divide by 16 filtering
100 = divide by 64 filtering
101 = divide by 256 filtering
110 = divide by 512 filtering
111 = divide by 1024 filtering
This would require some analog on the front end to resolve the sub-bit position, wouldn't it? Then, it would pwm, so to speak, the sub-bit position, so that the encoder could sum it up and gain another N bits of resolution. The normal count would start at bit N of the numerical output, and bits below N would be the fractional step. That would be pretty neat. The AB encoder would need to track time, not just state.