Program to determine Xtal Frequency - please try this for me :)
Cluso99
Posts: 18,069
Attached is a binary that should hopefully self-determine the crystal frequency and mode.
I am not sure whether this will always work due to the die process variations but its worth testing it out.
I am trying to determine crystals from 5.00MHz to 7.00MHz stepping every 0.25MHz, and 7.00MHz to 14.00MHz stepping every 0.5MHz.
I don't have all these crystals but with what I have it works, and I have extrapolated the others.
There is a 2s delay before the program runs to give you time to open up a serial terminal after downloading the program.
Here is a sample of what to expect.
If it woks, I will tidy and post the code
I am not sure whether this will always work due to the die process variations but its worth testing it out.
I am trying to determine crystals from 5.00MHz to 7.00MHz stepping every 0.25MHz, and 7.00MHz to 14.00MHz stepping every 0.5MHz.
I don't have all these crystals but with what I have it works, and I have extrapolated the others.
There is a 2s delay before the program runs to give you time to open up a serial terminal after downloading the program.
Here is a sample of what to expect.
FindFreq: Test the crystal frequency v0.10 *** Found Clock 104000000Hz, mode $6F, Crystal 6500000Hz, (116,219) FindFreq: Test the crystal frequency v0.10 *** Found Clock 104000000Hz, mode $6F, Crystal 6500000Hz, (115,219) FindFreq: Test the crystal frequency v0.10 *** Found Clock 96000000Hz, mode $6E, Crystal 12000000Hz, (211,0)
If it woks, I will tidy and post the code
Comments
Do you mean determine the crystal band grouping, for automatic correct VCO Divsion selection ?
as in ...
5MHz region Xtals use (Xtal x 16) / 1 -> SysCLK
10MHz region Xtals use (Xtal x 16) / 2 -> SysCLK
If you want to test something with *any* crystal value, I've found the Si5351A breakout from Adafruit useful.
It can output 3 different clocks to high precision, per program record sent via i2c.
Thanks for this. The range I have set for 5MHz is 160-169 where 170-179 is in my 5.25MHz range.
I need to see some more results to see if I can trim the ranges better, otherwise it is not going to work.
jmg,
Yes, I want to see how much variation there is between different dice.
Variable clock chips will not help here.
I'm not quite following ?
There will be significant variations between dice, and also with Vcc and Temperature of the VCO limits, so I would call 5.25MHz for a 5.00Mhz value actually quite good.
The best you can hope for is something like a '5MHz or 10Mhz' decision,
The VCO divide choices are only 2:1 anyway, so there seems not much need to be a lot finer ?
If you need much finer than that, you could get that from a BYTE received, for example.
On my G/G Propeller Platform
I am attempting to make my PropOS device and xtal independant so that I can release one binary for all prop/xtal sets (within a reasonable range). Here I often swap xtals. I can already detect all my pcb hardware so it shouldn't be hard to detect other common hardware. I am trying to avoid the alternative of auto-bauding on every power up (I have done this).
Btw the two results at the end of the message are clock count averages. If the second one is zero then you have a xtal operating at pll16x. (Over ~8MHz). If the second one is not zero then you are operating with pll8x and the first count should be ~162.
Anyone with a 6.25MHz or 10MHz xtal I would like to see what you get. I couldn't find all my box of xtals
Thanks
I do have my doubts that I can make this work successfully, but it is definitely worth trying it out as the benefits would be too good to pass up.
The only timing reference available that is common to all systems that I know of is the serial port used by the bootloader. Turn on the crystal without PLL perhaps and send a CR at 115200 baud and bingo!
The question is one of precision - With chip process variation, and away from the corners of extreme Vcc or Temperature, you should be able to decide 5MHz or 10MHz, but it is not clear exactly what precision the OP expects, or what 'work successfully' means ?
Trying to resolve between 5.25MHz or 5MHz with a free running, uncalibrated oscillator, I would call optimistic.
Using PC baud as calibrate, should resolve to under 1% at lowish baud rates on RC based bridges, and probably under 100ppm is possible on crystal based bridges.
eg We've done RC Calibrate sweeps on Silabs devices with a 15ppm LSB using a crystal based UART, but that's somewhat excessive precision as I was also looking at noise and jitter.
For example, there are a few base frequencies we use:
5, 6, (6.25), 6.5, 10, 12, (13.5) MHz.
Phils code can already determine the difference below 10MHz and equal/above.
While checking out his code I discovered some details about the pll in the counters. It seems that even with 5MHz & pllx16 the counter pll is not precise. However there is a range that it operates on. This range varies with xtal frequency.
Hence my effort to use this phenonom to see if I can reliably detect some different xtals, and how much process variations effect this.
BTW any xtals below about 8MHz with pll8 all lock successfully returning 162+/-1 and above 8MHz with pllx4 return the same.
I am only interested in general usage, not different voltages, etc.
If this works, auto-bauding will not be necessary. And what if the and keyboard are used and no serial where auto-baud img won't be available.
To resolve between 6.25MHz and 6.00 MHz is a ratio of
4%, so you expect/require the chip spreads to be better than 4%.
To me, that is (very) unlikely.
Even if it doesn't work for you (wrong baud giving rubbish).
Propeller Professional Development Board (5MHz Xtal)
FindFreq: Test the crystal frequency v0.10
*** Found Clock 84000000Hz, mode $6F, Crystal 5250000Hz, (116,171)
*** Found Clock 80000000Hz, mode $6F, Crystal 5000000Hz, (116,167)
Also, I was trying to figure out how I would go about this, and I have one idea, but it does require a pin. I could probably use the i2c SDA pin in a pinch, as the i2c bus shouldn't care as long as the clock isn't changing.
Jonathan
I would really like to see some 6.25MHz and 10MHz results please.
lonesock:
No other pins are used. My code just uses the an extended variation of the PLL Phil Pilgrim used in the video counters.
'' +--------------------------------------------------------------------------+ '' | FindFreq.spin: Try and determine the xtal being used v0.05 | '' +--------------------------------------------------------------------------+ '' | Authors: (c)2009 Philip C. Pilgrim (propeller@phipi.com) | '' | - original CLKSET.SPIN concept | '' | (c)2016 "Cluso99" (Ray Rodrick) | '' | - try and test for many crystal frequencies | '' | License: MIT License - See end of file for terms of use | '' +--------------------------------------------------------------------------+ '' 2009.05.23: Philip C. Pilgrim (propeller@phipi.com) '' WARNING: Trial, tentative, very alpha release! '' This object determines whether a 5MHz or 10MHz crystal is '' being used and sets the PLL accordingly for 80MHz operation. '' RR20160109 Cluso99: Try and determine many frequencies '' PLL16x 5.00MHz, 6.00MHz, 6.25MHz, 6.50MHz, 6.75MHz, 7.00MHz '' PLL8x 10.00MHz, 12.00MHz, 12.50MHz, 13.00MHz, 13.50MHz, 14.00MHz '' RR20160110 code to test and display result '' v0.07,8 seems to work for 5MHz '' v0.09 only report after found '' v0.10 forum test version { Results: (using averaging for count) XTAL CLKMODE PLLX CLKFREQ COUNT CLKMODE PLLX CLKFREQ COUNT CLKMODE PLLX CLKFREQ COUNT -------------------------------------------------------------------------------------------------------- 5.00 $6D 4X 20.00 116 $6E 8X 40.00 116 $6F 16X 80.00 167-168 6.00 $6D 4X 24.00 116 $6E 8X 48.00 116 $6F 16X 96.00 201-202 6.50 $6D 4X 26.00 $6E 8X 52.00 $6F 16X 104.00 218-220 7.37 $6D 4X 29.48 116 $6E 8X 58.96 121-122 $6F 16X 117.92 *too hi* -------------------------------------------------------------------------------------------------------- 10.00 $6D 4X 40.00 $6E 8X 80.00 $6F 16X 160.00 *too hi* 12.00 $6D 4X 48.00 116 $6E 8X 96.00 212 $6F 16X 192.00 *too hi* 13.00 $6D 4X 52.00 $6E 8X 104.00 $6F 16X 208.00 *too hi* 13.50 $6D 4X 54.00 116 $6E 8X 108.00 227-228 $6F 16X 216.00 *too hi* 14.00 $6D 4X 56.00 *too hi* *too hi* *too hi* } CON ' Please select the following for your board and compile & download & run pst (there is a 5 sec delay for this) ' Warning - we have to set it high or else it goes out of spec! ' _clkmode = xtal1 + pll16x ' _xinfreq = 5_000_000 ''''''''''' 5.00MHz 80MHz ' _xinfreq = 6_000_000 ''''''''''' 6.00MHz 96MHz ' _xinfreq = 6_250_000 ''''''''''' 6.25MHz 100MHz ' _xinfreq = 6_500_000 ''''''''''' 6.50MHz 104MHz ' _xinfreq = 6_750_000 ''''''''''' 6.75MHz 108MHz ' _xinfreq = 7_000_000 ''''''''''' 7.00MHz 112MHz ' _xinfreq = 7_370_000 ''''''''''' 7.37MHz 1??MHz _clkmode = xtal1 + pll8x ' _xinfreq = 10_000_000 '''''''''''10.00MHz 80MHz _xinfreq = 12_000_000 '''''''''' 12.00MHz 96MHz ' _xinfreq = 12_500_000 '''''''''''12.50MHz 100MHz ' _xinfreq = 13_000_000 '''''''''''13.00MHz 104MHz ' _xinfreq = 13_500_000 '''''''''''13.50MHz 108MHz ' _xinfreq = 14_000_000 '''''''''''14.00MHz 112MHz rxPin = 31 'serial txPin = 30 baud = 115200 OBJ fdx : "FullDuplexSerial" VAR long freq PUB main | f8, f16, savemode, savefreq, newmode, newfreq, newxtal waitcnt(cnt + clkfreq*2) savemode := clkmode '\ save original savefreq := clkfreq '/ ' first test with PLL8X 40_000_000 newmode := $6E newfreq := 40_000_000 clkset(newmode, newfreq) waitcnt(cnt + clkfreq/1000) f8 := findfreq ' test case f8 110..119 : ' 116+/- = within range so step to pll16x ' passed first test so try with PLL16X 80_000_000 newmode := $6F newfreq := 80_000_000 clkset(newmode, newfreq) waitcnt(cnt + clkfreq/1000) f16 := findfreq ' test again waitcnt(cnt + clkfreq/100) case f16 160..169 : clkset(newmode, 80_000_000) ' xtal 5.00MHz 167-168 170..179 : clkset(newmode, 84_000_000) ' xtal 5.25Hz ~175 180..189 : clkset(newmode, 88_000_000) ' xtal 5.50Hz ~185 190..199 : clkset(newmode, 92_000_000) ' xtal 5.75Hz ~195 200..203 : clkset(newmode, 96_000_000) ' xtal 6.00MHz 201-202 204..214 : clkset(newmode, 100_000_000) ' xtal 6.25MHz ~210 214..223 : clkset(newmode, 104_000_000) ' xtal 6.50MHz 218-220 224..231 : clkset(newmode, 108_000_000) ' xtal 6.75MHz ~228 232..238 : clkset(newmode, 112_000_000) ' xtal 7.00MHz ~235 other : clkset(savemode, savefreq-1) ' unknown - back to default !!!!!!!!!!!!!!! 120..123 : clkset(newmode, 58_960_000) ' xtal 7.37MHz 121-122 123..127 : clkset(newmode, 60_000_000) ' xtal 7.50MHz ~124? 128..137 : clkset(newmode, 64_000_000) ' xtal 8.00MHz ~133? 138..147 : clkset(newmode, 68_000_000) ' xtal 8.50MHz ~143? 148..157 : clkset(newmode, 72_000_000) ' xtal 9.00MHz ~153? 158..167 : clkset(newmode, 76_000_000) ' xtal 9.50MHz ~163? 168..177 : clkset(newmode, 80_000_000) ' xtal 10.00MHz ~173 178..187 : clkset(newmode, 84_000_000) ' xtal 10.50MHz ~183 188..197 : clkset(newmode, 88_000_000) ' xtal 11.00MHz ~193 198..207 : clkset(newmode, 92_000_000) ' xtal 11.50MHz ~203 208..214 : clkset(newmode, 96_000_000) ' xtal 12.00MHz 212 215..220 : clkset(newmode, 100_000_000) ' xtal 12.50MHz ~217 221..225 : clkset(newmode, 104_000_000) ' xtal 13.00MHz ~223 226..229 : clkset(newmode, 108_000_000) ' xtal 13.50MHz 227-228 230..235 : clkset(newmode, 112_000_000) ' xtal 14.00MHz ~232 other : clkset(savemode, savefreq-1) ' unknown - back to original newmode := clkmode ' save our new setting newfreq := clkfreq ' save our new setting case (newmode & $0F) $0F : newxtal := newfreq >> 4 ' pll16x $0E : newxtal := newfreq >> 3 ' pll8x { clkset(savemode, savefreq) ' restore the original } waitcnt(cnt + clkfreq/1000) fdx.start(rxPin,txPin,0,baud) ' restart with new clkmode/clkfreq setting fdx.str(string(13,"FindFreq: Test the crystal frequency v0.10",13)) fdx.str(string("*** Found Clock ")) fdx.dec(newfreq) fdx.str(string("Hz, mode $")) fdx.hex(newmode,2) fdx.str(string(", Crystal ")) fdx.dec(newxtal) fdx.str(string("Hz, (")) fdx.dec(f8) fdx.tx(",") fdx.dec(f16) fdx.tx(")") fdx.tx(13) waitcnt(cnt + clkfreq/10) fdx.stop pri findFreq '' Automatically test the pll mode to try and determine the crystal frequency freq~ cognew(@entry, @freq) repeat while (freq == 0) ' wait for cog to return result return (freq) DAT org 0 entry movi ctra,#%0_00001_011 'Set ctra for pll on no pin at x1. movi frqa,#%0100_0000_0 'Set frqa for clk / 4 (= 20MHz w/ 10MHz crystal, i.e. too high). add x,cnt 'Give PLL time to lock (if it can) and stabilize. waitcnt x,#0 movi vcfg,#$40 'Configure video for discrete pins, but no pins enabled. mov vscl,#$20 'Set for 32 clocks per frame. ***** waitvid 0,0 'Wait once to clear time. :again mov acc,#0 mov loops,loopcnt :loop neg x,cnt 'Read -cnt. waitvid 0,0 'Wait 32 pll clocks = 128 processor clks. add x,cnt 'Compute elapsed time. add acc,x ' add to accumulator djnz loops,#:loop shr acc,loopdiv ' divide by number of loops wrlong x,par ' pass count to spin cogid x 'Stop the cog: we're done. cogstop x x long $1_0000 '65536 clks for pll to stabilize. acc long 0 loops long 0 loopcnt long 256 '16 '\ loopdiv long 8 '4 '/ DAT {{ +------------------------------------------------------------------------------------------------------------------------------+ | TERMS OF USE: MIT License | +------------------------------------------------------------------------------------------------------------------------------+ |Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation | |files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, | |modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software| |is furnished to do so, subject to the following conditions: | | | |The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.| | | |THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE | |WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR | |COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | +------------------------------------------------------------------------------------------------------------------------------+ }}FindFreq: Test the crystal frequency v0.10
*** Found Clock 104000000Hz, mode $6F, Crystal 6500000Hz, (116,220)
In my tests maxing out the PLL, it seems to run at about 225 MHz, and of course it is fed by the NCO * 16, so the NCO needs to be running at or above 14 MHz. So if the actual system clock speed is any slower than 28 MHz I can't use this technique. (Which unfortunately means I can't get a decent read on RCFAST)
Jonathan
I am not quite sure what this means. Does it mean that the counter PLL cannot lock with an internal 80MHz clock??? It certainly appears so.
Take the 5MHz x16 example...
I set 5MHz x8 (40MHz internal clkfreq) and test the counter PLL. If it locks then I reliably get 116 as a result (thats the first of the numbers I output in the message).
If I get 116 +/- (110..119) then I proceed to set x16 and obtain the counter results again.
From this second result, I can determine roughly the xtal frequency (clkfreq) ranges. This is the second number I output)
'' Using the PLL hardware at max, estimate the clock. '' PLL max is about 225 MHz, so the NCO is /16 or 14 MHz. '' Meaning, any clock speed < 28 MHz can not be determined PUB approx_clock_Hz : Hz ' use counter A in PLL Video mode, running as fast as it can (~225 MHz / 128 = 1.76 MHz) ctra := constant( ( {PLL video mode} %00001 << 26) | ( {PLLDIV = 128} %000 << 23) ) frqa := constant( 1 << 31 ) ' PLL is fed by NCO * 16, and this is the fastest I can make it go ' set up the video mode: vga, color mode 0 (doesn't matter) vcfg := constant( %01 << 29 ) vscl := 0 ' PixelClocks = (0)256, only this matters => FrameClocks = 4096 (1.76 MHz / 4096 = 429 Hz) ' time how long it takes between waitvid's waitvid( 0, 0 ) Hz := -cnt waitvid( 0, 0 ) Hz += cnt ' turn everything off ctra := frqa := vcfg := vscl := 0 ' do the math Hz *= 425I just try to run the PLL as fast as absolutely possible. For any clockspeed below about 28 MHz the PLL can actually lock on, which is bad for my purposes. However, above a clockspeed of 28 MHz the PLL can't lock and it just runs as fast as possible. The PLL maxes out at about 225 MHz, with the PLLDIV at 128 that's 1.76 MHz, then I set the video hardware to use FrameClocks of 4096, meaning the frequecy at which it accepts waitvids is about 429 Hz. If I count the actual system clocks that elapsed between two consecutive waitvids, then multiply by 429 I have a decent approximation of the clock speed. On the system I was testing 425 actually gave a closer result than 429, so that's why it's still in the code. I see the PLL speed drift by about 1% or so as the PLL warms up.Thanks for the idea to use video mode! I had been using a pin previously, which was inelegant.
Jonathan
I would really like some more testing please !
I want to publish a boot program/module/object that can automatically detect and set the crystal/frequency used
And add some generic 5meg platforms also.
6.250 MHz xtal:
FindFreq: Test the crystal frequency v0.10
*** Found Clock 104000000Hz, mode $6F, Crystal 6500000Hz, (116,216)
6.000 MHz xtal:
FindFreq: Test the crystal frequency v0.10
*** Found Clock 100000000Hz, mode $6F, Crystal 6250000Hz, (116,206)
5.000 MHz xtal:
FindFreq: Test the crystal frequency v0.10
*** Found Clock 84000000Hz, mode $6F, Crystal 5250000Hz, (116,171)
4.9152 MHz xtal:
FindFreq: Test the crystal frequency v0.10
*** Found Clock 84000000Hz, mode $6F, Crystal 5250000Hz, (116,171)
4.000 MHz xtal:
(didn't like it. I'm not surprised!)
My code ignores anything below 5MHz so I expect that 4MHz would fail. Interesting all those frequencies were found to be .25MHz higher.
With more results hopefully I can tweek the ranges to reliably differentiate between common use values.
FindFreq: Test the crystal frequency v0.10
*** Found Clock 80000000Hz, mode $6F, Crystal 5000000Hz, (116,163)
PPDBoard:
FindFreq: Test the crystal frequency v0.10
*** Found Clock 84000000Hz, mode $6F, Crystaì 5250000Hz, (116,170)
Those numbers at the end tell me the counts so I can determine the range/spread in various props..
Hydra Board 10.0 MHZ XTAL
FindFreq: Test the crystal frequency v0.50
*** Found Clock 76000000Hz, mode $6E, Crystal 9500000Hz, (162,0)
Hydra Board 6.25 MHZ XTAL
FindFreq: Test the crystal frequency v0.50
*** Found Clock 100000000Hz, mode $6F, Crystal 6250000Hz, (116,204)
Hydra Board 5.00 MHZ XTAL
FindFreq: Test the crystal frequency v0.50
*** Found Clock 80000000Hz, mode $6F, Crystal 5000000Hz, (116,162)
QuickStart Rev A 5.00 MHZ XTAL
FindFreq: Test the crystal frequency v0.10
*** Found Clock 80000000Hz, mode $6F, Crystal 5000000Hz, (116,167)
EDIT: I changed the SPIN file to reflect the Revision Number in the Serial Output.
I also had to comment out
so the output would stay on the screen.