How does PLL generate 80 MHz from a 5 MHz crystal?

cbmeeks

I've read the Wikipedia article but it just isn't sinking in.

And I get that 5 * 16 = 80 but how does the PLL circuitry actually produce a signal that is 16 times its input?

Thanks!

kwinn

The output signal from a voltage controlled oscillator is divided (by 16 in this case) and compared to the input signal (5MHz in this case). The voltage that controls the oscillator is generated by the phase difference between the 5MHz input and the signal out of the divide by 16 circuit. After a short period the control voltage will cause the /16 signal to match (lock on to) the 5MHz input. At that point the output of the VCO is 80MHz.

tonyp12

It works by "tricking" a voltage follower type OSC,
It's trying to match its own voltage/phase but as its output goes through a /16 divider it will create a signal that is 16x as what it's trying to match.

Seairth

I think I finally see how this thing works! In the video, what was throwing me off was when it put the /2 circuit on the output of the VCO. That meant that it was outputing 3KHz, not 6KHz. But that's where the Phase Detector comes in! The 6KHz vs 3KHz input will cause a pulse train (through the filter) that would increase the voltage to the VCO, which would then increase it's frequency. The circuit will settle when the output of the /2 circuit matches the input frequency (6KHz, in this case), which means that the VCO will be running at 12KHz, or twice the input frequency!

Ramon

Hi cbmeeks,

As Kwinn have said.

The answer is not on the "PLL" page, the answer is on the "Frequency multiplier" page.

It is the VCO that is already running at around 80 MHz, and the PLL just only compares both clock phases and apply "voltage" feedback.

Phil Pilgrim (PhiPi)

The free-running frequency of the VCO appears to be in the 140-150 MHz range. The control voltage from the phase comparator lowers this frequency to lock (after division by 16) to the incoming crystal oscillator frequency and phase.

-Phil