Early VGA drivers
Ariba
Posts: 2,690
in Propeller 2
After playing with NTSC on my DE0-Nano, I tried to make some VGA drivers.
There is no description of the color modulator so far, but fortunately it's very similar to the old P2-hot. So I managed to get scaling and sync working.
With a 50 MHz clock the best fit is 640x480 standard VGA, because you can use a pixel frequency of 25 MHz.
I tried different streamer modes, and the RFBYTE RGBI8 allows to generate color bars very easy. Color bars are better than pictures to judge the quality of the driver, and they need very few memory, which is important for the Nano.
In the attached ZIP is a colorbar driver and a bitmap driver with 320x240 pixels signaled as 640x480. The bird-picture is very pixelated, as I had to reduce the resolution to 256x96 to make it fit in the 32kB memory of the DE0-Nano.
Andy
There is no description of the color modulator so far, but fortunately it's very similar to the old P2-hot. So I managed to get scaling and sync working.
With a 50 MHz clock the best fit is 640x480 standard VGA, because you can use a pixel frequency of 25 MHz.
I tried different streamer modes, and the RFBYTE RGBI8 allows to generate color bars very easy. Color bars are better than pictures to judge the quality of the driver, and they need very few memory, which is important for the Nano.
In the attached ZIP is a colorbar driver and a bitmap driver with 320x240 pixels signaled as 640x480. The bird-picture is very pixelated, as I had to reduce the resolution to 256x96 to make it fit in the 32kB memory of the DE0-Nano.
Andy
320 x 240 - 10K
zip
20K
Comments
So I would be interested in what you may come up with given your limited ability to test on the DE0.
For that I have made it. Perhaps you have noticed that I used the same names for all the variables as the NTSC drivers does, so a merge should be easy :thumb:
Andy
Doesn't work with DE2-115 though. Maybe VGA connections are different?
Doesn't work on P123-A7 either...
I wonder if Chip needs to connect the sync signals to FPGA outputs...
I just looked at P123 schematic and can't figure it out...
Hsync should be on one of the DACs (I think DAC0), and Vsync is on PA0. Perhaps you can test the signals at the VGA connector and the headers with a scope.
As far as I know with the P2-hot image the VGA drivers were compatible for DE0-Nano and DE2-115.
Andy
AFAIK they are not yet implemented in the P123-A7 FPGA image.
That's correct. You can't generate sync signals for VGA, yet.
On the next release, I'll make VGA HSYNC go high when DAC0 is not 0. I'll also make VGA VSYNC a regular pin. This will give complete VGA ports to cogs 0 and 1. On both cogs, DAC0 will be reduced to a digital output. This will enable VGA, but still work for TV and HDTV signalling, as well.
Maybe your monitor doesn't need vsync?
Or, maybe something is wrong with my setup...
It's an LG 1080p LCD Monitor/TV
Latest filenames end in _v4c.extension.
I think Chip made two updates with the same 15 or 15b number, or perhaps, 15, 15a, 15b, but the filenames differ, so check for that ending and you won't go wrong.
--> It works! Don't know what was the problem before though...
The photo is 8-bit bitmap with a special palette.
The output actually doesn't use the palette, it's just the RRRGGGBB direct mode...
Used Photoshop to set the palette and do some error diffusion to make it look good.
This is on DE2-115. There's not enough RAM for the whole photo.
Hopefully Chip will get us new P123 images with VGA enabled soon...
First, looks like nibble order is backwards. Not sure what to do about that...
Also, the bottom line is messed up. I don't think it's a memory issue,,
Have you got a picture of the 4bpp image using the file I posted for you that properly arranges the bitfields (nibble swap, in this case)?
(It actually looks better in the photo than it does on the screen... On the screen, the pixilation is much more noticeable compared to 8-bit per pixel...)