Embed small FPGAs in designs
koehler
Posts: 598
Embedding FPGA's in SOC/uC's appearing shortly?
http://semiaccurate.com/2015/10/30/flex-logic-embeds-small-fpgas-designs/
"The basic part is a FPGA, interconnect, and IO block which is called the EFLX-2.5K when built on TSCM 28HPM. In this guise it takes 1.1mm^2 and give the implementor 2520 LUTs, 5040 flip-flops, 8 clocks, 632 inputs, and 632 outputs. "
Comments
Mask costs are very high, and this does represent added risk to a project.
Really big players will know what they need, and can easily insert their own custom logic-remap if they need limited reconfig.
FPGA companies are already making FPGAs, so they are not customers.
MCU companies might consider it, but this is not for small MCUs and the FPGA companies already have hard coded ARMs on board, as well as DSP.
I have not even mentioned tools, and tool support yet...
Standalone CPLDs are modest in price, tools are free.
I can think of one possible area : Memory companies could offer what is mainly memory, with some FPGA.
Of course, they could do pretty much the same thing with a dual die package, for less risk.
Another problem is their process nodes are heavily memory tuned, and this IP is likely not available on the node they use.
- and I see this on today's news feed
["Processes, packaging, and interconnect are all shifting.
The term SoC implies a single-chip integration. But developments in interconnect and packaging technology are making multi-die implementations an important alternative across a much wider range of systems—if you plan for them."]
I've already started with Altera and Lattice, and that seems to be an awful lot to learn. Lattice seems to market quite a few small devices that I might consider using with the Propeller one day.
Just thought it was interesting, however the big players will all roll their own so to speak.
I'd like to get into the FPGA scene, however thinking maybe CPLD might be a simpler path to start.
Read up on the companies that are major players. Altera is #1, Xilin is #2.
https://en.wikipedia.org/wiki/Field-programmable_gate_array
Lattice is #3 in the FPGA market with about 7% market share, small enough for my support. The free provided software is really really important. It seems smaller makers are unable to provide as much for free as they too depend on buying software licenses.
I have an XP2 Brevia2 that was quite reasonable and programs via a USB interface... less than $100 USD. It is suppose to easily load ep16 Forth which is free, but I have been muddling through the author's typos. I soon hope to have that work. If that gets done, I could just share the binaries for loading.
Yes you can get much smaller devices that will do bits of logic. But you may soon tire of that and want something that does a complete microcontroller.
Lattice also has there own microcontroller example that will load on the same. 8 bit and 32 bit version.
My plan is to start with a specific implementation (here's prop 1 in FPGA) make one or two changes (here's a prop with more cores and more memory implemented in FPGA ), then add one specific circuit (here's a prop with specialized sensor circuit implemented in FPGA). I don't know if its a GOOD plan, but at least I'm not spending $$$ on parts that sit in the drawer until I ... ooh, shiny, I should buy one...
Lattice have a range of CPLD Boards for sub $30 and Altera have the new MAX 10 boards.
Lattice Mach Breakouts seem to all use a FT2232H, one channel for JTAG and the other for a user UART link.
If you want to use CPLD (or small FPGA) in production, it may pay to look forward to package choices & power supplies needed.
MAX 10 is 0.5mm QFP144, & they added 36 UFBGA and 81 UFBGA recently.
MachXO2 have QFN32, and QFP100/TQFP144 then all others are BGA
That leaves something of a package gulf between the small, and ~ QFP100, unless BGA is included
I see the new Lattice iCE40Ultra have QFN48, but these are OTP devices (tho they can also configure from SPI or MCU).
http://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40Ultra.aspx#_2BC6BD88F5C0403A907E053CFCD1195B
These QFN48 parts need 71,255 Bytes of Config.
iCE40Ultra could pair well with P1, for "adding a couple of custom COGs".
I checked the LUT counts against reported P1V builds of Xilinx_LUT at ~1404/COG, Max10_LUT ~1850/COG, so 2 COGs could be tight - more likely use is 1 COG and a decent amount of peripheral logic.
The Eval ICE5LP4K-B-EVN is $56.25 at Mouser, so is more costly than MachXO2/XO3 boards, and ICE5LP4K-B-EVN uses a 36 pin part, seems to pre-date the QFN48 ?
Hopefully, Lattice will release an EVN with QFN48.
Addit: On the [small FPGA+MCU] front, I see there is a $59.95 Eval Module, with 10k logic elements and a 166 MHz ARM Cortex-M3 with 256KF - only thing missing, is no expansion RAM on the board.
http://www.em.avnet.com/en-us/design/drc/Pages/Microsemi-SmartFusion2-KickStart-Development-Kit.aspx
Wonder how many P1V cogs can fit into that Logic ?
Altera just announced a new Ver 15.1 of Quartus II. Sadly it seems like that now desire you to pay for IP Cores as an add-on to the Free version. My impression was the IP Cores library was previously included as Free. That is what you need to build hubram.
And this is really the software feature I desire for small projects. It just allows you to check off a module rather than create from scratch. Just about anything your heart desires.
The eval board is cheap at $29.00.
The biggest version can host a 68k SOC solution along with VGA. Of course it can't host a resource monster like Prop. But it's a good CPLD/FPGA to learn on outside of that.
Or you can get a MAXII board off ebay for $8 and change and use them to experiment and learn.
To me, yhe best approach with mid-sized CPLDs is to include a P1 and the CPLD, and then you only really need one COG to support the special peripherals you have placed in the CPLD.
One recent topic example was fast quadrature counters.
Hits a SW ceiling in P1, but a P1V can support a Dozen
The Lattice XO2 goes up to 7000 LUTs ( I have no idea how Altera LE's compare with Lattice LUTs) but it's enough to host a 68K SOC solution like a Atari ST on it. So I would assume it can hold a Cog.
Or you can also implement a soft-core like a Mico8 which only takes up around 200 LUTs or a NIOS that uses 600 LE's. Both fit in their respective CPLD's - Lattice XO2 and Altera MaxII or Max V lines.
There is a whole range of FPGA/CPLD, so designers can match whatever they desire.
Remember, this is programmable logic, and a serial port is going to be trivial, and does not have to be Async-duplex. SPI and fast i2c are also possible.
I see this on Altera's website- isn't MegaCore IP Library what you need, and that is still free ?
Quartus Prime software Lite edition*
FREE, no license required
Includes MegaCore IP Library
IP available for purchase
*The Quartus Prime software Lite edtion version 15.1 supports the following device families: Arria II, Cyclone IV, Cyclone V, MAX II, MAX V, and MAX 10 FPGA.
Starting with version 15.1, Quartus II Web Edition is now Quartus Prime Lite Edition.
The PR seems focused on Arria, has anyone seen speed gains on Cyclone V or MAX 10 ?
I am USING a eP16 Forth VHDL design that requires it. It has worked sometimes, and at other times in has not (it locks up the computer). I still haven't gotten what I wanted.
But it does appear that the V15.1 is making some effort to charge money for the same as IP Basics. The language is unclear in the V15.1 promotion. What is MegaCore IP library? Is that a new name for the Megatrends IP Core library?
I really cannot keep up with all this 'cute marketing nonsense'. If something keeps changing its name, it is hard to follow with any continuity in learning.
++++++++++
Since Altera will NOT talk to anybody that doesn't register with them through a company name, there is no dialogue pass for clarification. I have to just read and guess what they mean or blunder through search engines in hopes of a good answer.
I read
Includes MegaCore IP Library
IP available for purchase
as meaning one now has to by this code library.
And to make matters more absurd, I can't seem to find a price for the added feature.
Basic Functions
DSP
Interface Protocols
Memory Interfaces and Controllers
Processors and Peripherals
University Program
Here are details of the stuff you have to pay for:
https://www.altera.com/products/intellectual-property/ip.html#processorsandperipherals
The headings might look similar to the ones for the free functions, but the functions are different.
The Lattice XO2 comes with built-in SPI and I2C(2) and timer hardware. Then add a couple UART's and you're ready to rock and roll.
A single Cog with interrupt capability should be able to manage all of them since it's not wasting time emulating them. Or just use another soft core to manage them if adding interrupts to the cog architecture is to hard.
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