RDBYTES/WRBYTES
Seairth
Posts: 2,474
in Propeller 2
How about we don't try to name it. Instead, add
RDBYTES D/#, S/#/ptr, #n
WRBYTES D/#, S/#/ptr, #n
xxBYTE, xxWORD, and xxLONG would just be aliases for N=1, 2, and 4 respectively.
I'm not quite following - Chip said this would be a PNUT ASM change, but your example suggests a packed reading of 3 bytes
( with presumably a matching Ptr+3 ). That's more than an Assembler change ?
I forgot about that. How is that going to work? encode it as a RDLONG+SHR?
The more I think about this, the more I would prefer that Chip support two general instructions for hub read/write in the P2, not just in PNUT:
CCCC 10110nn CZI DDDDDDDDD SSSSSSSSS RDBYTES D/#, S/#/ptr, #n CCCC 110001n nLI DDDDDDDDD SSSSSSSSS WRBYTES D/#, S/#/ptr, #n
As I mention in my comment (from the TYTES thread), #n would be a number between 1 and 4. The existing xxBYTE/xxWORD/xxLONG would just be aliases for this instruction.
You could also do the same with RFBYTES/WFBYTES
CCCC 1101011 CZ0 DDDDDDDDD 0000100nn RFBYTES D/#, #n CCCC 1101011 00L DDDDDDDDD 0000101nn WFBYTES D/#, #n
This reinforces the byte-oriented nature of hub memory, gives Peter his 24-bit read/write capability, and still allows for the old syntax. No need for tytes.
Comments
This I think is an excellent idea from the point of view of number of bytes, though I think it may be time consuming in the verilog for pointer indexed varients, as instead of either adding for one byte, and shifting for word and long, the three byte solution would require a shift and add. I hope it could be done in time from clock cycle point of view, or perhaps the three byte version would become a two instuction clock varient?
If we were earlier in the design phase, I would even have RDBITS/WRBITS, and make them the only way.