RCL/RCR/ROL/ROR inconsistent with P1
Seairth
Posts: 2,474
P1
C : first bit shifted out
P2
C : last bit shifted out
C : first bit shifted out
P2
C : last bit shifted out
Comments
Someone who has an FPGA should file an inconsistency if they find an instruction that still exhibits the P1 behavior.
We probably need a general statement from Chip on this.
Do you mean in cases of more than one-bit-shift ?
I'd expect multiple bits to behave like a chain of RCLs, which would mean the last shifted bit is in C.
In the P1 the spec states (in many of the instructions) that the C is set using the Source b[0] or b[31] depending on the instruction.
On the P2, this was fixed to mean the last bit shifted/rotated out.
Perhaps some instructions are using the Destination b[0] or b[31], which would also be a fixup from P1.
Some instructions set C as odd parity in the Destination.
PASM will require porting from P1 to P2 no matter what, I think P2 should strive for the best options rather than be saddled with P1 compatibility.
This also makes me think that we need a table/grid that states these differences between P1/P2.
Started. You can find (and modify) the list at:
https://docs.google.com/document/d/1O27nO2tMjBTvUNblFFRtEp5DHvcvsSGXcPvH9FaJ9u8/edit#bookmark=id.n1suwwbjxuk4