Using SETEDG for locks (and other event stuff)
Seairth
Posts: 2,474
in Propeller 2
While waiting for a resolution to the SETWRL issue, I tried changing my code to use locks instead. This mean using SETEDG. Unfortunately, this ended up breaking other code because... I was already using SETEDG for pin input!
Would it be possible to move the lock behavior to a separate SETLCK? The SETEDG opcode could still be used, but we would need a POLLLCK and WAITLCK (there appears to be space for these).
Because this would require a 4-bit configuration for SETINTx, I'd also suggest adding two more timers (or at least one more). This would require an additional ADDCNTx, POLLCNTx, and WAITCNTx per timer, but it appears there is space for those as well.
Would it be possible to move the lock behavior to a separate SETLCK? The SETEDG opcode could still be used, but we would need a POLLLCK and WAITLCK (there appears to be space for these).
Because this would require a 4-bit configuration for SETINTx, I'd also suggest adding two more timers (or at least one more). This would require an additional ADDCNTx, POLLCNTx, and WAITCNTx per timer, but it appears there is space for those as well.
Comments
Incidentally, the additional timer request came about as a result of a new FDS driver I am working on (pending the RDL/WRL fix). I really like the simplicity of it, except for one part: when either RX or TX is active, I basically have to spin in a busy loop waiting for the next tick interval. Because TX and RX are asynchronous, doing this with a single timer is problematic (to say the least). By adding at least one more timer, I can let the hardware sort out which event (RX or TX) needs to occur next. Even if it doesn't allow a faster baud rate than what I currently have, it will be much more power efficient! I think.
Note: the request for a total of three timers was just because there are a maximum of three interrupts. I can see a use case for dedicating a cog to nothing but timers. Otherwise, only two timers are necessary for what I have in mind for FDS.