PLL's in Cyclone V and P2

jmg

For when a PLL FPGA build is available, the PLL details are going to matter.

There are some code apps where 50MHz is not going to fit.
eg for 48 or 96MHz USB numbers from 50MHz, /5 for 10MHz fPFD and 960MHz VCO covers 96MHz /10 and 48Mhz /20

 --------------   Cyclone V PLL  ---------------

fIN -> /N  -> [PFD] <- /M <- [VCO] -> /C -> SysCLK
                |              |
                +------>-------+

/M,/N,/C counter sizes = /1 to /512

fIN Input clock frequency
–C6 speed grade 5 — 670(52) MHz
–C7, –I7 speed grades 5 — 622(52) MHz
–C8, –A7 speed grades 5 — 500(52) MHz
fINPFD Integer input clock frequency to the phase frequency detector (PFD) — 5 — 325 MHz
fFINPFD Fractional input clock frequency to the PFD — 50 — 160 MHz
fVCO PLL voltage-controlled oscillator (VCO) operating range
–C6, –C7, –I7 speed grades 600 — 1600 MHz
–C8, –A7 speed grades 600 — 1300 MHz

---

P2 PLL

---

/M,/N,/C counter sizes =
fINPFD phase frequency detector range (PFD) = ?
fVCO PLL (VCO) operating range = ?

Comments; The CV has a relatively high fPFD minimum, but also has a higher VCO
The P2 will likely have a lower fPFD lower limit, and also a lower VCO.

evanh

Is this topic leading anywhere?

jmg

evanh wrote: »

Is this topic leading anywhere?

Until a PLL FPGA build is available, I would expect it to be quiet
( I just had the DOC's opens from comments in another thread )