I started looking for similar concepts to "smart" that also fit with "propeller". Not much overlap there... but then it occurred to me that the name of the entire thing hasn't been set in stone either! So here's a proposal:
Chip: Parallax Percept
Pins: Perceptive I/O
Cogs: (can stay the same, but slightly different connotation)
Hub: (can stay the same)
There is definitely a bit of marketing going on here. You will notice that it still falls short of actual "perception", but still implies something related to intelligence. But that's where you can have some fun. How about this:
"Forever change your perception of what a microcontroller can do!"
"Perceive a whole new way of working with a microcontroller!"
"There is only one precept: Percept!"
Ha! Chip, you're a goof. I'm a fan of pun names, but I hope you're really sitting down to think of what the silliness of the names for the prop 2's new features might have on people's perception, and how the way you present P2 will affect the market response. To me, "fun" communicates "hobby"
A real propeller might have cogs but it also has busy little pistons pumping away.
PISTON - Processor IO System Task Operations Node
A propeller with 16 cogs and 64 pistons.....well my my...
It's great imagery. But...
I think we seriously run the risk of being too clever... too cute. There have already been a number of discussions about the difficulty of explaining this design to others. I think that we only make this worse if we get too clever with the "smart pin" name.
(note: Peter, this is not about your particular suggestion, rather the conversation overall.)
I need to come up with some assembly mnemonics that really pop, so the pin commands won't get lost in the source code. I mean, they configure and deal with whole subsystems, so they should stand out a little.
Don't try to correlate the mnemonics to the marketing name. Just start all of them with "X". As the first character in a word, that one tends to visually stick out. In fact, I think there are already some X-related instructions (XZERO, XINIT, XCONT). Others, like MSGIN/MSGOUT, could become XIN/XOUT or XMI/XMO.
Huh... I suppose you could could just call the pins "XPins". It doesn't really mean anything. Or... it actually could mean "anything", which is what these pins are capable of (as I/O pins go, that is).
Hmmm... is there any value in simply capturing a time stamp on an edge? We've got a single 32-bit return value to work with.
Yes. Capturing a time-stamp on edge would allow the smart-pins to do time-tagged photon counting. Useful for doing Lidar, Florescense lifetime spectroscopy, etc.
Question, will the smart-pin IO instructions be fast enough to capture the value of a free running counter every 50ns? Will there be enough instructions left between IO instructions to do a subtract, an array index, and an add? (i.e. the fastest portions of the photon counting system in the LIDARs I work on. currently done with an FPGA)
We have a 'propeller' chip that uses a propeller beanie cap for its logo, so why not keep it fun, instead of some nouveau-Italian-sounding name, like everyone seems to want? How about calling smart pins 'pinheads'? .... 'Pinhead' is a little comical and sets up realistic expectations, I think. "Only the Parallax Propeller has Pinheads." Anybody could remember that name, but nobody would want to copy it.
I quite favor using the name "pinhead." I contested a bit for this name at the following link by saying "[E]ach pin could be--dare I say it--a "pin head" or "pinhead." Each pin is a little brain in and of itself, separate from the COGS. Kind of matches the beanie, doesn't it (...)?"
I feel that this proposed "pinhead" term is compatible with the name "cog." I realize that a lot of folks want "cogs" referred to as "cores" in feature lists. That's fine, but the term "cog" can be retained alongside. And "pinhead" kind of seems like a natural complement to it. Imagine the illustration potential for the term "pinhead" in educational literature! Some might object that it's not "professional sounding" or whatever, but I'd bet that even professional engineers enjoy a little bit of playfulness as long as it doesn't come at the expense of understanding. In this case, it seems to me that the term "pinhead" helps to demarcate a useful distinction between cogs and the logic that is in the pins (at the head-end, so to speak), while at the same time connecting them under playful monikers that are easy to visualize/remember/convey. To set itself apart, it could be useful for Parallax to continue with its own creative nomenclature.
Sure, the proposed term may seem a bit self-deprecating, but I feel that it's "crazy like a fox." For me, the choice of "pinhead" as a distinct name for smart pins is, ahem, a no-brainer. But I'll be happy with a chip featuring such pins whatever they end up being called. It's great that we're getting so close that names are even being considered. Congrats on all the progress, Chip. Way to go! --Jim
PINJAS - Ninjas can do almost anything, apparently. Pinjas are like ninjas, for pins.
PINTENDO 64 - Each pin is attentively 'tended' to
or
JUGGLERS - jugglers keep stuff spinning separately from the main circus. For product launch and trade shows everyone at parallax will need to learn to juggle (I think Ken already can??)
PINJAS - Ninjas can do almost anything, apparently. Pinjas are like ninjas, for pins.
PINTENDO 64 - Each pin is attentively 'tended' to
or
JUGGLERS - jugglers keep stuff spinning separately from the main circus. For product launch and trade shows everyone at parallax will need to learn to juggle (I think Ken already can??)
Hmmm... is there any value in simply capturing a time stamp on an edge? We've got a single 32-bit return value to work with.
Yes. Capturing a time-stamp on edge would allow the smart-pins to do time-tagged photon counting. Useful for doing Lidar, Florescense lifetime spectroscopy, etc.
Question, will the smart-pin IO instructions be fast enough to capture the value of a free running counter every 50ns? Will there be enough instructions left between IO instructions to do a subtract, an array index, and an add? (i.e. the fastest portions of the photon counting system in the LIDARs I work on. currently done with an FPGA)
Marty
You're probably looking at 20 clocks to notice the event, grab the time stamp, and get ready for the next. As long as the pulses were spaced out at least that much, it would work.
One way to achieve better performance would be to have the streamer write a 32-bit time stamp to the hub via its WFLONG capability on each pin edge of interest. Edges could come at clock/2, or 80MHz, in the case of a 160MHz clock. Is this a novel feature? It would be very trivial to add.
Ha! Chip, you're a goof. I'm a fan of pun names, but I hope you're really sitting down to think of what the silliness of the names for the prop 2's new features might have on people's perception, and how the way you present P2 will affect the market response. To me, "fun" communicates "hobby"
Which in the past and likely still today equates to low volume and near-impossible recovery of NRE - unless the P2 is plopped into a very high volume module where we have margin and near-viral adoption.
But as time has passed I have also changed and see that more companies try to make their chips friendlier and more accessible with fun names. I officially won't be entering any horses in the race to name the Propeller subsystems, as all I really want is to see it completed.
And I think the emphasis is that the pin IS a peripheral in its own right. Every other chip has peripherals which they can route to some pins but that's so 2015....
Question, will the smart-pin IO instructions be fast enough to capture the value of a free running counter every 50ns? Will there be enough instructions left between IO instructions to do a subtract, an array index, and an add? (i.e. the fastest portions of the photon counting system in the LIDARs I work on. currently done with an FPGA)
Could be tight, above, Chip says it streams nibble wide, so 8 SysCLKS, so that just packs into 160MHz. and gives you a 8 CLK REP loop for the housekeeping.
One way to achieve better performance would be to have the streamer write a 32-bit time stamp to the hub via its WFLONG capability on each pin edge of interest. Edges could come at clock/2, or 80MHz, in the case of a 160MHz clock. Is this a novel feature? It would be very trivial to add.
Yes, that type of edge-stamp is very useful for Logic Analyzers too.
You need to capture the pin-level too, but I think above was mentioned 31 bits of time and 1 pin bit ?
Comments
...plus there's that Minion tie in..who doesn't like minions!!!
I started looking for similar concepts to "smart" that also fit with "propeller". Not much overlap there... but then it occurred to me that the name of the entire thing hasn't been set in stone either! So here's a proposal:
Chip: Parallax Percept
Pins: Perceptive I/O
Cogs: (can stay the same, but slightly different connotation)
Hub: (can stay the same)
There is definitely a bit of marketing going on here. You will notice that it still falls short of actual "perception", but still implies something related to intelligence. But that's where you can have some fun. How about this:
"Forever change your perception of what a microcontroller can do!"
"Perceive a whole new way of working with a microcontroller!"
"There is only one precept: Percept!"
Ha! Chip, you're a goof. I'm a fan of pun names, but I hope you're really sitting down to think of what the silliness of the names for the prop 2's new features might have on people's perception, and how the way you present P2 will affect the market response. To me, "fun" communicates "hobby"
intelipin?
now where have I seen those first five letters before?
Dave
PISTON - Processor IO System Task Operations Node
A propeller with 16 cogs and 64 pistons.....well my my...
It's great imagery. But...
I think we seriously run the risk of being too clever... too cute. There have already been a number of discussions about the difficulty of explaining this design to others. I think that we only make this worse if we get too clever with the "smart pin" name.
(note: Peter, this is not about your particular suggestion, rather the conversation overall.)
PIP - Pin I/O Peripheral
Superpin name is in use, but in a different context, I think...
I'm sure Chip can find another name...
Don't try to correlate the mnemonics to the marketing name. Just start all of them with "X". As the first character in a word, that one tends to visually stick out. In fact, I think there are already some X-related instructions (XZERO, XINIT, XCONT). Others, like MSGIN/MSGOUT, could become XIN/XOUT or XMI/XMO.
Huh... I suppose you could could just call the pins "XPins". It doesn't really mean anything. Or... it actually could mean "anything", which is what these pins are capable of (as I/O pins go, that is).
Yes. Capturing a time-stamp on edge would allow the smart-pins to do time-tagged photon counting. Useful for doing Lidar, Florescense lifetime spectroscopy, etc.
Question, will the smart-pin IO instructions be fast enough to capture the value of a free running counter every 50ns? Will there be enough instructions left between IO instructions to do a subtract, an array index, and an add? (i.e. the fastest portions of the photon counting system in the LIDARs I work on. currently done with an FPGA)
Marty
I quite favor using the name "pinhead." I contested a bit for this name at the following link by saying "[E]ach pin could be--dare I say it--a "pin head" or "pinhead." Each pin is a little brain in and of itself, separate from the COGS. Kind of matches the beanie, doesn't it (...)?"
forums.parallax.com/discussion/155132/the-new-16-cog-512kb-64-analog-i-o-propeller-chip/p13
I feel that this proposed "pinhead" term is compatible with the name "cog." I realize that a lot of folks want "cogs" referred to as "cores" in feature lists. That's fine, but the term "cog" can be retained alongside. And "pinhead" kind of seems like a natural complement to it. Imagine the illustration potential for the term "pinhead" in educational literature! Some might object that it's not "professional sounding" or whatever, but I'd bet that even professional engineers enjoy a little bit of playfulness as long as it doesn't come at the expense of understanding. In this case, it seems to me that the term "pinhead" helps to demarcate a useful distinction between cogs and the logic that is in the pins (at the head-end, so to speak), while at the same time connecting them under playful monikers that are easy to visualize/remember/convey. To set itself apart, it could be useful for Parallax to continue with its own creative nomenclature.
Sure, the proposed term may seem a bit self-deprecating, but I feel that it's "crazy like a fox." For me, the choice of "pinhead" as a distinct name for smart pins is, ahem, a no-brainer. But I'll be happy with a chip featuring such pins whatever they end up being called. It's great that we're getting so close that names are even being considered. Congrats on all the progress, Chip. Way to go! --Jim
PINTENDO 64 - Each pin is attentively 'tended' to
or
JUGGLERS - jugglers keep stuff spinning separately from the main circus. For product launch and trade shows everyone at parallax will need to learn to juggle (I think Ken already can??)
From: https://google.com/?gws_rd=ssl#q=synonyms+for+smart
Oh well, none of those sound quite right... "clever-pin"? "astute-pin"? "shrewd-pin"?... Egad! :zombie:
dgately
everything hinges on the.... 'kingpin'
Dave
It seems to fit nicely now with P2.
PION Programmable Input/Output Node
CIOP Configurable Input/output Pin
Still, I like "superpin" or "uberpin"...
Whoa! Jugglers!
"Pinjas" is good, too.
You're probably looking at 20 clocks to notice the event, grab the time stamp, and get ready for the next. As long as the pulses were spaced out at least that much, it would work.
One way to achieve better performance would be to have the streamer write a 32-bit time stamp to the hub via its WFLONG capability on each pin edge of interest. Edges could come at clock/2, or 80MHz, in the case of a 160MHz clock. Is this a novel feature? It would be very trivial to add.
Which in the past and likely still today equates to low volume and near-impossible recovery of NRE - unless the P2 is plopped into a very high volume module where we have margin and near-viral adoption.
But as time has passed I have also changed and see that more companies try to make their chips friendlier and more accessible with fun names. I officially won't be entering any horses in the race to name the Propeller subsystems, as all I really want is to see it completed.
Ken Gracey
I agree, good suggestion. Short descriptive, and not too far out there.
PINITO = pins finito
You need to capture the pin-level too, but I think above was mentioned 31 bits of time and 1 pin bit ?
or, something that explains more what the pin-cell is, along the lines of flexi-pin ?