Prop2 FPGA files!!! - Updated 2 June 2018 - Final Version 32i

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Comments

  • evanhevanh Posts: 10,087
    edited 2018-01-30 - 11:50:03
    Hmm, I don't set X or Y ... assumed to be all zeros ...

    EDIT: Good catch there Oz. Totally fixed that problem. Thanks.

    EDIT2: So the lesson there is any previous state bits of a Smartpin is retained through a new setup unless they're explicitly set.

  • Well, here's my latest dump of what I was really trying to achieve (At 80 MHz Sysclock):
    SmartPin mode = %01111, Count highs
    pin# reset     pause     high......later     low.......later
      9  00000000  00000000  00000000  00000002  00000002  00000004
         ---------\___________________/-------------------\_________00000026
      8  00000000  00000000  00000000  00000001  00000001  00000002
         ---------\___________________/-------------------\_________00000026
      7  00000000  00000000  00000000  00000001  00000001  00000002
         ---------\___________________/-------------------\_________00000026
      6  00000000  00000000  00000000  00000001  00000001  00000002
         ---------\___________________/-------------------\_________00000026
      5  00000000  00000000  00000000  00000001  00000001  00000002
         ---------\___________________/-------------------\_________00000026
      4  00000000  00000000  00000000  00000001  00000001  00000002
         ---------\___________________/-------------------\_________00000026
      3  00000000  00000000  00000000  00000002  00000002  00000004
         ---------\___________________/-------------------\_________00000026
      2  00000000  00000000  00000000  00000002  00000002  00000004
         ---------\___________________/-------------------\_________00000026
      1  00000000  00000000  00000000  00000002  00000002  00000004
         ---------\___________________/-------------------\_________00000026
      0  00000000  00000000  00000000  00000002  00000002  00000004
         ---------\___________________/-------------------\_________00000026
    

    And (At 40 MHz Sysclock):
    SmartPin mode = %01111, Count highs
    pin# reset     pause     high......later     low.......later
      9  00000000  00000000  00000000  00000001  00000001  00000002
         ---------\___________________/-------------------\_________00000026
      8  00000000  00000000  00000000  00000001  00000001  00000002
         ---------\___________________/-------------------\_________00000026
      7  00000000  00000000  00000000  00000001  00000001  00000002
         ---------\___________________/-------------------\_________00000026
      6  00000000  00000000  00000000  00000001  00000001  00000002
         ---------\___________________/-------------------\_________00000026
      5  00000000  00000000  00000000  00000001  00000001  00000002
         ---------\___________________/-------------------\_________00000026
      4  00000000  00000000  00000000  00000001  00000001  00000002
         ---------\___________________/-------------------\_________00000026
      3  00000000  00000000  00000000  00000001  00000001  00000002
         ---------\___________________/-------------------\_________00000026
      2  00000000  00000000  00000000  00000001  00000001  00000002
         ---------\___________________/-------------------\_________00000026
      1  00000000  00000000  00000000  00000001  00000001  00000002
         ---------\___________________/-------------------\_________00000026
      0  00000000  00000000  00000000  00000001  00000001  00000002
         ---------\___________________/-------------------\_________00000026
    
  • evanhevanh Posts: 10,087
    edited 2018-01-30 - 12:15:33
    At 80 MHz, Smartpin's #4 through #8 are faster acting than the others.

    EDIT: In other words, what affects Chip's example here http://forums.parallax.com/discussion/comment/1426177/#Comment_1426177 is also affecting the much tighter Smartpin circuit.

    Which means the supposedly long run routes aren't causing any issues.

  • Here's my full source for the above dumps. You'll need a terminal set to 115kbps to capture its dump. I use Dave's loadp2.

  • Evan
    Did you try other clock speeds?

    @60 Mhz (HUBSET #$BF)
    SmartPin mode = %01111, Count highs
    pin# reset     pause     high......later     low.......later
      9  00000000  00000000  00000000  00000001  00000001  00000003
         ---------\___________________/-------------------\_________00000026
      8  00000000  00000000  00000000  00000001  00000001  00000002
         ---------\___________________/-------------------\_________00000026
      7  00000000  00000000  00000000  00000001  00000001  00000002
         ---------\___________________/-------------------\_________00000026
      6  00000000  00000000  00000000  00000001  00000001  00000002
         ---------\___________________/-------------------\_________00000026
      5  00000000  00000000  00000000  00000001  00000001  00000002
         ---------\___________________/-------------------\_________00000026
      4  00000000  00000000  00000000  00000001  00000001  00000002
         ---------\___________________/-------------------\_________00000026
      3  00000000  00000000  00000000  00000001  00000001  00000003
         ---------\___________________/-------------------\_________00000026
      2  00000000  00000000  00000000  00000002  00000002  00000003
         ---------\___________________/-------------------\_________00000026
      1  00000000  00000000  00000000  00000001  00000001  00000002
         ---------\___________________/-------------------\_________00000026
      0  00000000  00000000  00000000  00000001  00000001  00000003
         ---------\___________________/-------------------\_________00000026
    
    
    
  • Peter JakackiPeter Jakacki Posts: 9,813
    edited 2018-01-30 - 23:43:53
    @ozpropdev - If I use $BF for instance I end up with a very slow jitter so that the frequency sits close around 60MHz but it's not steady as it is with the pure binary dividers.

    btw - $9F seems to be jitter free at 50MHZ.

    My test setup is to output a 1MHz signal on a pin and then hubset and observe the frequency and jitter. My system always responds to a serial break so I can easily restore control to my console.
    1 PIN 1 MHZ
    $9F HUBSET
    
    The other way to read it easier is to output 80 kHz and then read kHz as MHz on the scope.
  • evanh wrote: »
    Smartpin #0 doesn't work on my Prop123_A9 board using v31 of 8-Cog image. Here's the mode I'm using:
    wrpin   ##%0100_0000_011_0000000000000_01_01111_0, #tpin   ' A=OUT B=pin F=A^B M=Count highs
    
    Z never changes from a value of zero.

    Using same code on pins 1 through 4 always gives a non-zero result. I'm software pulsing the OUT line with a OUTH, take a reading, then OUTL, and another reading.

    I'm at the same time sampling the neighbour's IN, which is configured to show me what the test pin's state is.
    wrpin   ##%0111_0000_000_0000000000000_00_00000_0, #tcnt   ' A=(pin-1)  M=normal input
    
    This IN still works as expected and shows me the issued OUT is arriving at the physical pin (#0) under test.

    After the WRPIN, Did you do the 'WYPIN #0,#0' to count A-highs.

    And what about the WXPIN to establish the period?

    I'm thinking there might be some old X and Y states left over after booting.
  • @ozpropdev - If I use $BF for instance I end up with a very slow jitter so that the frequency sits close around 60MHz but it's not steady as it is with the pure binary dividers.

    btw - $9F seems to be jitter free at 50MHZ.
    Peter
    To be honest I hadn't noticed the jitter in my limited tests at different speeds.
    I ran Chip's VGA 640 * 480 demo from 30MHz to 80 MHz in the 5 MHz steps and it all seemed to work Ok.
    My monitor might be compensating (hiding) any jitter.
    I did the same in a basic serial Tx test from 5 to 80 MHz to verify the 5MHz steps.
    All my testing otherwise runs at the max 80MHz. :)

  • cgracey wrote: »
    I'm thinking there might be some old X and Y states left over after booting.

    Yep. That's exactly what it was. Oz got me sorted there.

    Now the real timing issue with the pins needs sorted. Or at least confirmed that the final ASIC won't have the same differences between pins.
  • evanh wrote: »
    cgracey wrote: »
    I'm thinking there might be some old X and Y states left over after booting.

    Yep. That's exactly what it was. Oz got me sorted there.

    Now the real timing issue with the pins needs sorted. Or at least confirmed that the final ASIC won't have the same differences between pins.

    Differences between pins? What do you mean? The ASIC will be like the FPGA with 8 cogs, 512K hub, and 64 smart pins.
  • evanhevanh Posts: 10,087
    edited 2018-01-31 - 00:43:20
    Have a careful look at these posts on this page.
  • evanh wrote: »
    Have a careful look at these posts on this page.

    Ah, you mean timing paths getting stretched into the next clock, right?

    The ASIC's timing will be tighter, but to get really exact timing, turn on the clocked modes (WRPIN ##%0000100000000<<8,#pin). The clocked modes register input and output states right on the pin, itself.
  • Thanks, that is probably all that's needed. I didn't think any of the P field was operational in the FPGA.

    I'm at work at the moment ... so will be some hours to test.


  • evanh wrote: »
    Thanks, that is probably all that's needed. I didn't think any of the P field was operational in the FPGA.

    I'm at work at the moment ... so will be some hours to test.


    The C, I, and O bits (P[8..6]) are supported.
  • Hasn't helped at all. :( In fact there is even more variations now.

    But maybe the most interesting part is it appears to be 100% repeatable. Each run produces the same set of answers. Even Oz posted identical results to me.

    Take a look at pins 1 and 2 below. The rise propagation time differs from the fall propagation time but each rerun is completely consistent. It doesn't seem to be a borderline case.
    SmartPin mode = %01111, Count highs
    pin# reset     pause     high......later     low.......later
      9  00000000  00000000  00000000  00000004  00000004  00000008
         ---------\___________________/-------------------\_________00000026
      8  00000000  00000000  00000000  00000003  00000003  00000006
         ---------\___________________/-------------------\_________00000026
      7  00000000  00000000  00000000  00000003  00000003  00000006
         ---------\___________________/-------------------\_________00000026
      6  00000000  00000000  00000000  00000003  00000003  00000006
         ---------\___________________/-------------------\_________00000026
      5  00000000  00000000  00000000  00000003  00000003  00000006
         ---------\___________________/-------------------\_________00000026
      4  00000000  00000000  00000000  00000003  00000003  00000006
         ---------\___________________/-------------------\_________00000026
      3  00000000  00000000  00000000  00000004  00000004  00000008
         ---------\___________________/-------------------\_________00000026
      2  00000000  00000000  00000000  00000003  00000003  00000007
         ---------\___________________/-------------------\_________00000026
      1  00000000  00000000  00000000  00000003  00000003  00000007
         ---------\___________________/-------------------\_________00000026
      0  00000000  00000000  00000000  00000004  00000004  00000008
         ---------\___________________/-------------------\_________00000026
    
  • evanhevanh Posts: 10,087
    edited 2018-01-31 - 08:26:08
    Here's the new Smartpin config:
    wrpin   ##%0100_0000_011_0000100000000_01_01111_0, tpin ' A=OUT B=pin F=A^B P=registered M=Count highs
    

    Here's a dump of the lower 60 61 Smartpins. Physical pins 55-57 ($37-$39) seem to be stuck high so that the Z counter accumulates while OUT is low. Maybe a faulty board.

    Everything else is fitting what we expect for the moment.
    SmartPin mode = %01111, Count highs
    pin# reset     pause     high......later     low.......later
     3c  00000000  00000000  00000000  00000003  00000003  00000006
     3b  00000000  00000000  00000000  00000003  00000003  00000006
     3a  00000000  00000000  00000000  00000003  00000003  00000006
     39  00000001  01323e45  01334f7b  01334f7d  01334f7d  013460bf
     38  00000001  01323e45  01334f7b  01334f7d  01334f7d  013460bf
     37  00000001  01323e45  01334f7b  01334f7d  01334f7d  013460bf
     36  00000000  00000000  00000000  00000003  00000003  00000007
     35  00000000  00000000  00000000  00000003  00000003  00000006
     34  00000000  00000000  00000000  00000003  00000003  00000006
     33  00000000  00000000  00000000  00000003  00000003  00000006
     32  00000000  00000000  00000000  00000003  00000003  00000006
     31  00000000  00000000  00000000  00000003  00000003  00000006
     30  00000000  00000000  00000000  00000003  00000003  00000006
     2f  00000000  00000000  00000000  00000003  00000003  00000006
     2e  00000000  00000000  00000000  00000003  00000003  00000006
     2d  00000000  00000000  00000000  00000003  00000003  00000006
     2c  00000000  00000000  00000000  00000003  00000003  00000007
     2b  00000000  00000000  00000000  00000003  00000003  00000006
     2a  00000000  00000000  00000000  00000003  00000003  00000006
     29  00000000  00000000  00000000  00000003  00000003  00000006
     28  00000000  00000000  00000000  00000003  00000003  00000006
     27  00000000  00000000  00000000  00000003  00000003  00000006
     26  00000000  00000000  00000000  00000003  00000003  00000007
     25  00000000  00000000  00000000  00000003  00000003  00000006
     24  00000000  00000000  00000000  00000003  00000003  00000006
     23  00000000  00000000  00000000  00000003  00000003  00000007
     22  00000000  00000000  00000000  00000003  00000003  00000007
     21  00000000  00000000  00000000  00000003  00000003  00000006
     20  00000000  00000000  00000000  00000003  00000003  00000007
     1f  00000000  00000000  00000000  00000003  00000003  00000006
     1e  00000000  00000000  00000000  00000003  00000003  00000006
     1d  00000000  00000000  00000000  00000003  00000003  00000006
     1c  00000000  00000000  00000000  00000003  00000003  00000006
     1b  00000000  00000000  00000000  00000003  00000003  00000006
     1a  00000000  00000000  00000000  00000003  00000003  00000006
     19  00000000  00000000  00000000  00000003  00000003  00000006
     18  00000000  00000000  00000000  00000003  00000003  00000006
     17  00000000  00000000  00000000  00000003  00000003  00000006
     16  00000000  00000000  00000000  00000003  00000003  00000006
     15  00000000  00000000  00000000  00000003  00000003  00000006
     14  00000000  00000000  00000000  00000003  00000003  00000006
     13  00000000  00000000  00000000  00000003  00000003  00000006
     12  00000000  00000000  00000000  00000003  00000003  00000006
     11  00000000  00000000  00000000  00000003  00000003  00000006
     10  00000000  00000000  00000000  00000003  00000003  00000006
     0f  00000000  00000000  00000000  00000003  00000003  00000006
     0e  00000000  00000000  00000000  00000003  00000003  00000006
     0d  00000000  00000000  00000000  00000003  00000003  00000006
     0c  00000000  00000000  00000000  00000003  00000003  00000006
     0b  00000000  00000000  00000000  00000003  00000003  00000006
     0a  00000000  00000000  00000000  00000003  00000003  00000006
     09  00000000  00000000  00000000  00000004  00000004  00000008
     08  00000000  00000000  00000000  00000003  00000003  00000006
     07  00000000  00000000  00000000  00000003  00000003  00000006
     06  00000000  00000000  00000000  00000003  00000003  00000006
     05  00000000  00000000  00000000  00000003  00000003  00000006
     04  00000000  00000000  00000000  00000003  00000003  00000006
     03  00000000  00000000  00000000  00000004  00000004  00000008
     02  00000000  00000000  00000000  00000003  00000003  00000007
     01  00000000  00000000  00000000  00000003  00000003  00000007
     00  00000000  00000000  00000000  00000004  00000004  00000008
    
  • Evan
    Pins 57..55 are wired to the pushbuttons on the P123-A9 board.
  • Ah, okay, thanks. That's not very obvious.

  • evanh wrote: »
    Ah, okay, thanks. That's not very obvious.
    Yes this caught me out early on.
    Pins 57..55 input/outputs are split.
    The outputs are routed to the header and the inputs are routed to the pushbuttons.


  • cgraceycgracey Posts: 13,122
    edited 2018-01-31 - 10:34:06
    Evanh, you are seeing varying numbers of cycles in your measurements, when you should have a consistent value, since your tests are all identical, right? I haven't loaded any of your code, yet, but I'm wondering if you get inconsistent results even at low frequencies. Is that the case?

    Perhaps turning on clocking doesn't cause a timing simplification, because one logic cone just replaces another.

    I might be able to remedy this by making timing assignments on the I/O pins, like I had to for the DACs. I just did so and am compiling now.
  • Oh, no, that's only for 80 MHz. At 40 MHz all pins read identically. Here's a new 40 MHz run:
    SmartPin mode = %01111, Count highs
    pin# reset     pause     high......later     low.......later
     09  00000000  00000000  00000000  00000003  00000003  00000006
         ---------\___________________/-------------------\_________00000026
     08  00000000  00000000  00000000  00000003  00000003  00000006
         ---------\___________________/-------------------\_________00000026
     07  00000000  00000000  00000000  00000003  00000003  00000006
         ---------\___________________/-------------------\_________00000026
     06  00000000  00000000  00000000  00000003  00000003  00000006
         ---------\___________________/-------------------\_________00000026
     05  00000000  00000000  00000000  00000003  00000003  00000006
         ---------\___________________/-------------------\_________00000026
     04  00000000  00000000  00000000  00000003  00000003  00000006
         ---------\___________________/-------------------\_________00000026
     03  00000000  00000000  00000000  00000003  00000003  00000006
         ---------\___________________/-------------------\_________00000026
     02  00000000  00000000  00000000  00000003  00000003  00000006
         ---------\___________________/-------------------\_________00000026
     01  00000000  00000000  00000000  00000003  00000003  00000006
         ---------\___________________/-------------------\_________00000026
     00  00000000  00000000  00000000  00000003  00000003  00000006
         ---------\___________________/-------------------\_________00000026
    
  • At 40 MHz:
    - With registered pins, it's 3 clocks per transition.
    - Without registered pins, it's 1 clock per transition.

    At 80 MHz,
    - With registered pins, it's 3 or 4 clocks per transition.
    - Without registered pins, it's 1 or 2 clocks per transition.
  • Okay. I think this is to be expected. The ASIC will not be this loosey-goosey. So, is there really a problem?
  • I'm trying to make a timing assignment for the I/O's, but I can't get proper hold of the clock yet, as it's named inside the PLL IP, only.
  • cgracey wrote: »
    Okay. I think this is to be expected. The ASIC will not be this loosey-goosey. So, is there really a problem?

    I guess I'm not clear about, confident, of that outcome. I can accept the Cogs having this but the Smartpins should be tight enough I'd have thought.
  • When I started the coding for this test, I wasn't actually expecting the Smartpins to show the same issue .... I'm now pondering what will happen if one smartpin toggles another.
  • evanh wrote: »
    cgracey wrote: »
    Okay. I think this is to be expected. The ASIC will not be this loosey-goosey. So, is there really a problem?

    I guess I'm not clear about, confident, of that outcome. I can accept the Cogs having this but the Smartpins should be tight enough I'd have thought.

    The inputs are all immediately registered when they come in from the pins. It's the outputs that may be causing this.

    If you stimulate PinA via the OUTA/OUTB bit, there should be no timing problem. Driving the pin to an output state and then echoing back that state is probably what is taking all the time. Can you please check that?
  • evanhevanh Posts: 10,087
    edited 2018-01-31 - 11:23:36
    The instructions used are OUTH and OUTL. I take readings for each. That's doing what you've asked I believe.

    The pin direction doesn't change for the duration of each pin being tested.

    The Smartpin compares (xor) the OUT signal (from the OUTH/L instruction) with the pin's input signal that follows. The number of clocks they are different for is the accumulated reading.
  • cgraceycgracey Posts: 13,122
    edited 2018-01-31 - 11:40:29
    If you were to use:
    wrpin   ##%0100_0000_000_0000000000000_01_01111_0, #tpin   ' A=OUT B=pin F=A M=Count highs
    

    Then you would be eliminating that analog round trip around the physical pin (in one clock) and you shouldn't see any weirdness at any frequency, because everything would be synchronous.

    This blurring is due to the analog pin being driven to a state via its output circuitry, then reading back through its input circuitry, in insufficient time to meet hold timing on the input register.
  • It looks like my timing assignments are absorbed, finally, so I'm recompiling for the Prop123-A9 with 8 cogs, 512KB, and 64 smart pins. I'll have this posted in the morning.
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