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P123 DAC's? — Parallax Forums

P123 DAC's?

rjo__rjo__ Posts: 2,114
in Propeller 2
The fact that I haven't figured this out is no surprise to me... but I have this vague concern that it might not be me:) And if there is a problem with the DACs... now would be the time to figure it out. And it doesn't look like the next P2 image is going to address this issue.

I have Verilog code to drive VGA, which was verified on a DE2-115(which requires a blanking signal... whereas this is not required on the P123 and which is really ugly and which I have previously posted... and which does not actually include a P1V . The code seems to work in that it generates a signal, which my monitor correctly interprets and displays to be... 800x600 RGB at 40MHz. Problem is the screen is black, even when I try to paint every pixel on every clock... although in the usual mode I am painting only at the correct time. The code drives DAC1_clk synchronously, with the output of 10 bit RGB pixel values to DAC1 . I took the pin assignments directly from Chip's pin assignments. I output hsync to expc[5] and vsync to expc[4]... which seems to be what Chip's PDF indicates.

So... from the monitor report of 800x600 RGB mode, I think I can conclude that these signals are reaching the monitor, but not the output of DAC1?

Comments

  • SeairthSeairth Posts: 2,474
    1. You are connected to VGA1?
    2. Do you have a scope to see if you are getting any output on the matching RCA sockets?
    3. Which PDF are you referring to?
    4. Is this a modified P1V you are using, or custom Verilog/VHDL code?
  • rjo__rjo__ Posts: 2,114
    1 yes
    2 no
    3 in the P123 stuff linked by Ken in his first post in the sticky thread at the top
    4 no p1v... just custom Verilog...I wanted to make sure it was working before adding in the P1v. I know the logic works because I took it out a working de2-115 project. And from the monitor report at the right top of the screen... the sync signals look like they are making it fine... but on the P123 these signals have nothing to do with the DACs... they directly routed to the VGA connector.





  • rjo__rjo__ Posts: 2,114
    I am basically looking for confirmation that someone has tested the DAC's and a description of what they did. If the dacs are working but there is a problem with the my VGA connectors, that would be fine, we can always use the other connectors:)

    Here is the RBF I used. VGA1
    zip
    zip
    P123D (2).zip
    108K
  • ozpropdevozpropdev Posts: 2,792
    edited 2015-09-26 03:38
    The schematic and QSF assignments are reversed?
    set_location_assignment PIN_A20 -to dac0_clk
set_location_assignment PIN_H10 -to dac1_clk
should be
set_location_assignment PIN_H10 -to dac0_clk
set_location_assignment PIN_A20 -to dac1_clk

    Edit: I built a P1V with both DAC's connected and neither DAC seems to work. I'll keep digging. :)

    Update: All DAC's wrking now, a silly typo tripped me up! :)
  • YanomaniYanomani Posts: 1,524
    Hi ozpropdev

    Have you programmed BANK7A pins to operate at 1.8V, departing from its nominal VCCPD of 2.5V?

    Henrique
  • ozpropdevozpropdev Posts: 2,792
    Yanomani
    Bamk7A are connected to the green leds on he Prop123-A7 board.
    They are currently set at 3.3V LVCMOS.
  • YanomaniYanomani Posts: 1,524
    edited 2015-09-26 04:22
    ozpropdev

    Sure they are connected to the green leds, but the leds are meant to be turned on by a low level at the output pin of the FPGA.

    In the schematic I have, downloaded from the first page of this thread, BANK7A VCCPD is connect to 2.5V.

    The DACs cannot operate with its digital inputs more than .5V above of its digital power supply, that, in turn, is connected to 1.8V.
  • ozpropdevozpropdev Posts: 2,792
    Yanomani
    You are correct.
    Tthe digital pins are being pushed 0.2V above the maximum ratings according to the datasheet.
    The DAC's are working now anyway because of the assignment error.
    The P123-A9 board needs this to be changed though.

  • YanomaniYanomani Posts: 1,524
    edited 2015-09-26 05:14
    ozpropdev

    Indeed, Cyclone V devices are very tricky to program.

    I saw in the schematics that VCCIO for BANK7A is set to 1.8V, but I'm unsure about all the necessary steps to program the pins interface voltage to meet the standard 1.8V CMOS levels, in order to ensure the connected DACs will not experiment a voltage swing they will not withstand comfortably.
  • cgraceycgracey Posts: 14,134
    The DACs have been working fine for me.

    If you are using Prop1 code, there might be a problem with needing to generate hsync outside of the old 2-bit resistor DAC arrangement. On the Prop2, because we don't have PLL's for the video, but use some division of the system clock, you must use exp_c pins to do hsync (and vsync) by making I/O pins high and low, under software control.
  • rjo__rjo__ Posts: 2,114
    Thanks Guys,

    I have the rug rat for the weekend... he used to take naps... no more.

    Rich
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