Microchip release 2MBF, 512kBR, 300MIP Floating point MCU

jmg

Up to 200 MHz, 330 DMIPS
Floating Point Unit
Up to 2 MB Flash with Live Update
Up to 512 KB SRAM
up to 12-bit, 18 MSPS ADC module with up to 48 channels and 6 S&H circuits
Hi-Speed USB 2.0 Host/Device/OTG
10/100 Ethernet MAC with MII/RMII Interfaces
2x CAN 2.0B Ports
Up to 6 UART (25 Mbps), 5 I2C™, 6 SPI Ports, and I2S
8 Channels of General Purpose DMA & up to 18 Channels of Dedicated DMA
External Bus Interface (EBI),
Serial Quad Interface (SQI), 50 MHz
Crypto Engine
64 to 144 pins
$7.96/5k for 2048k Flash 512k RAM model, 64pins $9.23/5k 144 pins

Some reference points there, for P2 to litmus-test against.

Similar (simpler) parts :
NUC505DL13Y Nuvoton M4 WITH 2MBYTE FLASH BASED $2.40/2k

Heater.

You mean like:
http://digilentinc.com/Products/Detail.cfm?NavPath=2,892,1266&Prod=CHIPKIT-WIFIRE#utm_medium=Press-Release&utm_term=PIC32MZEF Launch_PR_9-14-15&utm_content=MCU32&utm_campaign=chipKIT

The chipKIT Wi-FIRE dev board 79 dollars available 1st Oct.

Leon

Here are details of the chip used on that board:

http://www.microchip.com/wwwproducts/Devices.aspx?product=PIC32MZ2048EFG100

Low quantity pricing: http://www.microchipdirect.com/ProductSearch.aspx?keywords=PIC32MZ2048EFG100

jmg

The P2 needs to be able to talk to device like this, and above.
( see also the thread on FT600 for a slightly tougher interface )

*50 MHz External Bus Interface (EBI)
*50 MHz Serial Quad Interface (SQI)
*Six UART modules (25 Mbps):
*Six 4-wire SPI modules (50 Mbps)
*SQI configurable as an additional SPI module (50 MHz)
*Five I2C modules (up to 1 Mbaud) with SMBus support
*Parallel Master Port (PMP)

ie the DMA with P2 Burst and Smart pins, should be able to pump data at least at 50MHz over QuadSPI, or EBI/Parallel master Port.

A part like this has higher IO bandwidth than a Raspberry Pi.
With HS USB and Ethernet and CAN, it makes a good general bridge device.
Even the ADC is 'quite good' at 12b 18Msps.

Brian Fairchild

How many COGs would be used on a P2 to emulate that peripheral set?

jmg

Brian Fairchild wrote: »

How many COGs would be used on a P2 to emulate that peripheral set?

Good question.
Hopefully, with the right smart pins, pretty much anything simple-serial under 100MHz should be possible. (UART,SPI,QuadSPI,CAN,i2c,i2s)

HS USB @ 480MHz is clearly off the table, even fully compliant FS USB has question marks.
Ethernet MAC ? - also unclear. Perhaps ?

rod1963

Don't forget about benchmarking/comparing the CPU's on computationally intensive tasks. Cog vs. MIPS. Gentlemen ready your C compilers at 20 paces. Hopefully the PII is on par with the MIPS in terms of integer performance.