USB 3.0 & P2
jmg
Posts: 15,175
New release on USB 3.0, and just in time to be used with P2 images... 
A choice of 16b and 32b FIFO models.
http://www.ftdichip.com/Products/ICs/FT600.html
http://www.ftdichip.com/Corporate/Press/USB Brochure.pdf
PDF claims 3.2 GB/s bursting with configurable endpoint buffers of
16kByte length for IN and 16kByte for OUT.
Stocks seem to be real at RS, and due later this month at Digikey.
- no part codes showing for modules ? *
The fast HUB streaming modes (R & W?) should be able to burst 16b wide via some simple smart pin handshakes. Maybe 32b wide too ?
* Addit : Search for other than FT600Q finds these coming due 22 Sept.
768-1253-ND UMFT600A FTDI DEV BOARD FT600 USB3 16BIT FIFO 0 $71.04 1
768-1255-ND UMFT600X FTDI DEV BOARD FT600 USB3 16BIT FIFO 0 $71.04 1
A choice of 16b and 32b FIFO models.
http://www.ftdichip.com/Products/ICs/FT600.html
http://www.ftdichip.com/Corporate/Press/USB Brochure.pdf
PDF claims 3.2 GB/s bursting with configurable endpoint buffers of
16kByte length for IN and 16kByte for OUT.
Stocks seem to be real at RS, and due later this month at Digikey.
- no part codes showing for modules ? *
The fast HUB streaming modes (R & W?) should be able to burst 16b wide via some simple smart pin handshakes. Maybe 32b wide too ?
* Addit : Search for other than FT600Q finds these coming due 22 Sept.
768-1253-ND UMFT600A FTDI DEV BOARD FT600 USB3 16BIT FIFO 0 $71.04 1
768-1255-ND UMFT600X FTDI DEV BOARD FT600 USB3 16BIT FIFO 0 $71.04 1
Comments
Any links to that 'simple solution' ?
There are not many doing USB 3.0 interface devices, and less doing USB 3.0 FIFO Bridge parts...
?? That is only a FS solution, two generations of speed behind USB 3.
CP2110 is 1MBd or 125k Bytes/sec.
FT232H can do 12MBd or 30 MBytes/sec in FIFO modes, which is likely to be slower than P2.
FT600 is one of the few devices that P2 could hope to feed at full P2 Speeds.
For code download, you might tolerate the slower speeds, in exchange for avoiding drivers (although Parallax have not chosen to do that, for P1 or P2).
For working system interfaces, speed often trumps other luxuries.
If you need to pump large amounts of data, then you need the fastest links. Period.
That is where USB 3.0 comes in.
The P2 FPGA image should be tested with a FT600, the availability timing looks ok for that.
http://malwaretips.com/threads/ftdi-admits-to-bricking-innocent-users-chips-in-silent-update.35786/
OK, so we move them to 2nd place on the suppliers list.
That leaves you to suggest the replacement supplier, who has a USB 3.0 FIFO Bridge ?
As fas as I can tell USB 2 can shift something like 48 mega bytes per second. That's the entire content of P2 RAM nearly one hundred times per second.
USB 3 is cruising at 480 mega bytes per second. Or the entire content of P2 RAM nearly one thousand times per second.
Correct me if I am wrong I have not researched so hard.
Is it even possible to get data out of a PII and into a USB 3 chip at that speed? (Or the other way around?) Anyone got a handle on the answer to that question.
Where is this data going to come from anyway?
I may be a bit slow (pun intended) but I'm not seeing the need for or possibility of using USB 3 with the PII.
Anyway, on the plus side, in the name of progress, you have a great opportunity to be the first to produce a design for an FT600 break outboard or P2 + FT600 board and demo software objects.
If it works I might be tempted to turn a blind eye to FTDI's past transgressions. (If they have Open Source Linux drivers that is).
The P2 should be able to stream data well above 40MHz, and wider than 8 bits.
A classic bottle neck.
Hence that is where USB 3.0 comes in -
Larger buffers, and around 5x (Possibly 10?) the practical bandwidth is not to be ignored.
The FT232H is slower than the (current expected specs of) P2. But the FT600 is faster than the available througput of the P2. The FT600 has only two operation frequencies: 66 MHz or 100MHz (both with 16 bits wide bus). If I am not wrong, the P2 will need 4x 66MHz to feed the FT600 fifo. That means a P2 clocked a 264 MHz.
The sad true is that there is no replacement/susbtitute. The cypress FX3 is too complex. They have made amazing efforts to bring something easy to test. The book from John Hyde, the starter board for just only $49, and also the small xilinx coolrunner-II cpld daughter board (just $49 too) to test the FX3. I was tempted to buy both of them some time ago when I saw the differential traces (with matched impedance) on the CPLD board. It is an amazing testing board for high speed. But the complexities of the cypress FX3 (with an ARM CPU more powerful maybe than my current mobile phone) made me think twice.
I said (then) that FTDI will come with something simpler. And they did indeed. But while they have a nice and simple IC, they made the mistake of doing a complex development board only intented to be attached to medium or high-end ($$$) fpga boards with complex connectors (FMC-LPC and HSMC). Why they didn't made any effort to support low cost FPGA/CPLD boards (DE0-nano, Bemicro, Spartan-3/6) ?
So there is no other way to have high speed and simple interface. And FTDI has not yet said if they plan to make FT60x (D3XXX) drivers for other OS/Architectures (Linux x86, Linux ARM, Mac ... ) as they have with their FT232H (D2XX). That is another issue.
1) USB 3.0 FIFO bridge with simple protocol (like FTDI).
2) Drivers available for several OS/Architectures (WIN,Linux ... x86, ARM)
3) *Low clocked FIFO* (10/25 MHz) to allow the P1 or P2 (and any FPGA/CPLD) to do processing or ping-pong with the data.
4) *Low clocked FIFO* to avoid complex PCB layout and timing issues.
5) Simple development board with pin headers on FIFO side.
Thanks so much !!
(10MHz@16 bits is 20 MB/s. and 25MHz@32 bits is 100 MB/s.)
For data throughput, then of course you have an argument that the Silabs CP2110 may be too slow for some data. The solution I have moved to is to not put a USB connector direct on each Prop module, but to put a 4 pin Molex KK header. Then if needed, you can send the user a USB module that can have whatever type USB interface on it you want for whatever purpose. If you need high speed in a case where the user is willing to deal with the FTDI headaches the give them the FTDI. If you are only updating firmware once in a while, send them the Silabs part. I already have a proploader for the CP2110 for PC/Mac/Linux, in both standalone app for my purposes and as a console app that can be used by any other IDE. The new Proploaders would be slick if they allowed third party loaders. Which is a simple as
Compile
Save binary to disk as a temp file
Load the temp file into the command line app
Propram to prop
I do this now but it takes several steps and it really fast now that I have it organized. It is not really a big deal to save a binary, then have another app sitting there and hit LOAD FILE, UPLOAD TO RAM/EEPROM.
The bottom line is if there is a driver required, you are going to regret it on a consumer product.
It does need management of the details, but the numbers are not so bad.
The CLK from FT600 means
a) P2 will have to accept a 66MHz CLK into the PLL
That's probably ok, & should also be FPGA test-able.
This may also impose limits on PLL locked skews, which I have not seen defined yet ?
With the right attention to details, this should be able to be reduced.
ie operate the Phase Comparator so it tracks CLK->pin delays.
b) Spec gives Tsu of 2.3ns, and on 66MHz that leaves an inside-P2 turnaround of 12.851ns (full cycle pipeline) or 5.275ns (half cycle, SPI like )
That's probably also ok, but may need care right at the smart pins.
A small Pin-FIFO could relax the phase impositions here.
Chip has said burst streaming at up to SysCLK should be possible, and I would expect a pin-limit in the region of 100MHz
SysCLK/2 with a x2 PLL, would operate the P2 at 132MHz, FIFO @ 66MHz (just ok on FPFA ?)
SysCLK/3 and a x3 PLL would be 198MHz (FIFO @ 66MHz) - time will tell if that is likely.
Depending on the PLL design, and the Pin-FIFO+handshake there may be other solutions too.
eg 66MHz SysCLK, or 3/2 PLL for 99MHz SysCLK etc
Because the USB-FIFO is WR_N and RD_N qualified, my reading of the data allows slip cycles at any time, provided WR_N and RD_N respond.
That means the P2 core can feed slower, but the Smart-Pins need to be able to strobe RD_N, WR_N at the 66MHz speed.
I would think that both SW feed and HW streaming should both be possible, with average data rates << 66MHz but peak burst speeds up to 16k bytes of == 66MHz
Just in time to test with upcoming P2 images ...
2.0 looks adequate for 99% tasks out there.
3.0 doesn't make sense unless on the back end you have the P-II configured as a PCIe device with massive HDD streaming about 250 MB/Sec data to it. But I don't even know if a P-II could emulate a PCIe interface to begin with let alone working at full speed.
Lots of things need to be ironed out first.
Simple: Throughput and latency.
Sure, but the Prop2 does not target 99% of tasks out there
Prop 2 does have high bandwidth to pins, ao attention needs to be given to what can use that bandwidth.
Why PCIe ? The PC side does not care what is feeding the USB bus.
USB 2.0 is too slow to keep up with a P2 peak speed, and USB 2.0 devices have smaller buffer sizes.
USB 3 allows more bandwidth from a P2, to link to a PC Host, and the larger buffers allow more time between packet updates but still maintain continual streaming.
Where is all that data going to come from? Or go to?
What is the use case here?
Who said it has to reach peak USB 3 speeds ?
All that matters is that the USB link, does not limit what P2 can do.
If you look at the data, the FT600 has a FIFO bus at 100MHz or 66.6MHz & 16 bits wide.
That means the FT600 can do 133.2MBytes/s or 200Mbytes/s peak. (16k Buffers)
That is significantly above the FT232H speed, of 40 Mbytes/Sec (1k buffers)
That 40 MB/s is well below what P2 can do, so why limit a transfer to that ?
(Of course, implicit in this, is that FT600 FIFO support would also include FT232H FIFO support too.)
To use the streaming HW to talk to even a slower FT232H @ 40MB/s, is going to need some simple HW FIFO handshake state engine support.
FT600 support means allow FIFO of
*16 or 8 bits wide
* CLK speeds that include 40MHz, 66.6MHz, 100MHz
I'm not saying that USB 3.0 won't be useful, it's just that I haven't figured out the real numbers here.
(For the desktop, or maybe even more for small ARM boards like the Odroid boards, USB 3.0 gives significant advantage with nearly 1A out and the ability to attach gigabit ethernet adapters and USB 3.0 disk drives. For the P2 those use cases are not so relevant).
-Tor
those figures are given above,
IIRC, P2 can stream at up to SysCLK (NCO based), and at widths of 4?/8/16/24 for LCD displays.
SysCLK speeds of 100/120/150/180 have all been mentioned, (time will tell) but I would also expect pins to limit the top end practical numbers to ballpark ~100MHz.
The highest speed needed for support FT600 is 100MHz, so that matches quite nicely.