How have people been doing it with P1v on the 1-2-3 A7 board?
Cancel my reply above - from the other thread it seems P1V were erratic, and do improve with the resistor-add.
( A SMD poked under the corner seems a solution )
After all the PLL drama, I've got Prop2 comfortably running on the Prop 1-2-3 FPGA -A7 board.
This is a much simpler setup than the DE2-115. Everything is on one board, there's no need for a PropPlug, just one USB connection. Download is 15x faster, and there's no need to cycle power, just flip a PGM/RUN switch.
15x speedup sounds delicious... Is the programming and pin usage exactly the same for the A9 as the A7? I wonder if I should dig into the BeMicroCV-A9 schematic and the 1-2-3 schematic and see how hard it would be to drop a Propeller on the BeMicroCV-A9 for programming... Is that worth the trouble?
===Jac
The -A9 actually has 16 fewer I/O pins. For this reason, the -A9 board will write to each video DAC on different edges of the clock. So, we saved pins by muxing the 3x10-bit data inputs to the DACs.
I need to get a BeMicro -A9 board to make configuration files for it.
After all the PLL drama, I've got Prop2 comfortably running on the Prop 1-2-3 FPGA -A7 board.
This is a much simpler setup than the DE2-115. Everything is on one board, there's no need for a PropPlug, just one USB connection. Download is 15x faster, and there's no need to cycle power, just flip a PGM/RUN switch.
That sounds encouraging. Are you likely to release an A7 image before the new A9 board is ready? Might still be worth picking up an A7 board after all.
Edit: I just realized that you're probably talking about the 1-2-3 A7 board with the whisker wire. Is there any other way to get a clock to the P2? How have people been doing it with P1v on the 1-2-3 A7 board?
I'll first make an image for the Prop123 -A7 board, which seven people have, already. Then, I'll do the DE2-115. Then, probably the DE0-Nano (1 cog) with the add-on board we had built earlier.
After all the PLL drama, I've got Prop2 comfortably running on the Prop 1-2-3 FPGA -A7 board.
This is a much simpler setup than the DE2-115. Everything is on one board, there's no need for a PropPlug, just one USB connection. Download is 15x faster, and there's no need to cycle power, just flip a PGM/RUN switch.
That sounds encouraging. Are you likely to release an A7 image before the new A9 board is ready? Might still be worth picking up an A7 board after all.
Edit: I just realized that you're probably talking about the 1-2-3 A7 board with the whisker wire. Is there any other way to get a clock to the P2? How have people been doing it with P1v on the 1-2-3 A7 board?
I'll first make an image for the Prop123 -A7 board, which seven people have, already. Then, I'll do the DE2-115. Then, probably the DE0-Nano (1 cog) with the add-on board we had built earlier.
Sounds good. Will the Prop123-A7 image require the soldered on resistor for the PLL or is there another way to make the clock work?
There's also provision for an external clock via SMA connector. The Adafruit Si5351 board jmg linked to would work well with that, and goes to 160 MHz. $8 + $2.50 for the SMA connector, then all you need is an sma to sma rf lead, which are easy enough to get
So far, OzPropDev has the only board that works straight up, vs 4 which don't, and a few more yet to know. Perhaps there are a few others in that batch of 30 that work straight up like OzPropDev's
There's also provision for an external clock via SMA connector. The Adafruit Si5351 board jmg linked to would work well with that, and goes to 160 MHz. $8 + $2.50 for the SMA connector, then all you need is an sma to sma rf lead, which are easy enough to get
So far, OzPropDev has the only board that works straight up, vs 4 which don't, and a few more yet to know. Perhaps there are a few others in that batch of 30 that work straight up like OzPropDev's
Thanks for the info. I guess I'm lazy and am looking for a solution that doesn't require soldering parts to the board or plugging in another module. I guess I'll wait for the A9 board or, more likely, just use the DE2-115 or DE0-Nano images.
It'd be great to get you, and others who made solid contributions to P2, involved earlier rather than later, if possible.
If its just 1 soldered resistor stopping you, then we have to help get that sorted. I'm happy to help where practical
Given Ken's A9 timing prediction, and assuming an A7 image is days rather than weeks away, it'll likely be mainly the A7 that helps flush out bugs and other usage issues. Its also possible we'll find further things that further delay the A9, once we get stuck into the A7.
Today I worked out some subtleties involving the debug interrupt and I found and fixed a bug in the RDLONG-wrlut instruction. I also got those 9-bit relative branch addresses to be long-offset, not byte-offset.
Mainly, though, my time was spent organizing the Verilog code to make it manageable and easy to look at. One thing that has helped a lot is having two 4k monitors turned 90-degrees into portrait mode. It's so much better to be able to see almost 200 lines of code at once, per monitor. It gives a whole new perspective on everything and makes it really easy to navigate. If you think about it, if you work through a peephole of 40 lines of code all the time, it is requisite that your brain maintains a mental image of the bigger picture. With 200 lines of code in your face, it's way less taxing on the mind.
You can see from line 729 the two 8-long programs that run on the cog to perform a cold start and coginit-induced start. On line 749 you can see where the instruction is picked from either the lut_q or the reg_qx (1st port of the dual-port cog ram), based on p[11], which is the program counter bit that crosses from $7FC (cog) to $800 (lut).
This business of making programs so that you can see more of them at once is really important. I've been thinking for years about how this can be done, besides increasing rows and columns. If we could make some kind of 2.5-dimensional representation, that might be a part of it. It would be neat if, at a glance, you could see your whole code - not necessarily legibly, but recognizably as a 2+dimensional shape that you could maybe spin into the desired perspective to edit it.
... I also got those 9-bit relative branch addresses to be long-offset, not byte-offset.
Good to hear. It had crossed my mind that this was a potential issue the moment you said everything is viewed as byte addressing now, at least from the programming model view.
If you think about it, if you work through a peephole of 40 lines of code all the time, it is requisite that your brain maintains a mental image of the bigger picture. With 200 lines of code in your face, it's way less taxing on the mind.
Totally. My one big coding project I've done I was given a textmode folding editor. I didn't think anything of it at the time but it didn't take long before I had created layers of folds, particularly for the GUI structures. The editor stored the folded state of each fold in the source ... not to mention features like multiple views of the same file. In hindsight, I now recognise how much the text editor mattered for development manageability when limited to just a single 40 line display.
One thing that has helped a lot is having two 4k monitors turned 90-degrees into portrait mode. It's so much better to be able to see almost 200 lines of code at once, per monitor. It gives a whole new perspective on everything and makes it really easy to navigate. If you think about it, if you work through a peephole of 40 lines of code all the time, it is requisite that your brain maintains a mental image of the bigger picture. With 200 lines of code in your face, it's way less taxing on the mind.
Wow! That looks like a great workspace. 4K monitors aren't even that expensive these days. What kind of video card did you need to drive these monitors?
Wow! That looks like a great workspace. 4K monitors aren't even that expensive these days. What kind of video card did you need to drive these monitors?
Some card with two DisplayPort connectors. It wound up dictating a new motherboard. So, it was twice as expensive as we anticipated. After a bit, I went back to 1920x1080 resolution because it made everything easier to read, like the menu bars. Right now, though, I've gone back to 3840x2160 because I'm mainly looking at text. Portrait mode is really nice. I just didn't realize, at first.
Back in the day awe would print our source on that wide green ruled fanfold line printer paper. As long as you like. Then you get a good view of your creation.
I remember one guy who tended to write long functions with very deep 'if' levels and the like.. once I had to wait until everybody else had left so that I could roll a printout of his program from one end of a very long corridor to the other. Fanfold paper of course, try that with sheets from the laser printer..
This was in the mid-eighties. Got his code sorted out though (later I rewrote it to something smaller..)
Well of course. If you put everything into a single function then you know where everything is
I did once manage to prune a function on 3 of those fanfold pages to just two lines. My colleague out did me he got it down to one line. We decided to go with my version as it was actually readable.
I have an ASUS USB monitor that I often use in portrait mode for text. USB 3 is fast enough for text. I would not game on it. Gives me 2560 vertical, 1920 horizontal.
Maybe I'll buy a second one.
The Sublime editor has a "greeked" version of code on the right side for the purpose of seeing the whole thing as a rough shape.
Nice screens, Chip! I put my monitor into portrait mode sometimes - it does give a different perspective on things!! Sure is better than reading code one line at a time from a deck of cards!!!
Re: Si5351 breakout solution - that's a really nice I2C programmable clock chip. I've ordered the board and connectors but haven't found the cables yet. Being a programmable clock, it needs something to talk to so you can set it up and get it running. It looks like I may need to build a little "clock box" for my bench out of the breakout board and a spare Arduino (quickest solution since Adafruit has a sketch already).
I remember less than 20 years ago a 19" VGA 800x600 monitor (CRT of course) cost $2,500 wholesale.
Still have a couple of boxes of fanfold paper - only good for grandkids to draw on now
It'd be great to get you, and others who made solid contributions to P2, involved earlier rather than later, if possible.
If its just 1 soldered resistor stopping you, then we have to help get that sorted. I'm happy to help where practical
Given Ken's A9 timing prediction, and assuming an A7 image is days rather than weeks away, it'll likely be mainly the A7 that helps flush out bugs and other usage issues. Its also possible we'll find further things that further delay the A9, once we get stuck into the A7.
regards
Lachlan
Thanks but I think the DE2-115 will be fine for what I'll be doing.
15x speedup sounds delicious... Is the programming and pin usage exactly the same for the A9 as the A7? I wonder if I should dig into the BeMicroCV-A9 schematic and the 1-2-3 schematic and see how hard it would be to drop a Propeller on the BeMicroCV-A9 for programming... Is that worth the trouble?
===Jac
The -A9 actually has 16 fewer I/O pins. For this reason, the -A9 board will write to each video DAC on different edges of the clock. So, we saved pins by muxing the 3x10-bit data inputs to the DACs.
I need to get a BeMicro -A9 board to make configuration files for it.
I went through the BeMicro-A9 schematics and it looks like it's not possible to connect the Propeller to download the binary in the same way as on the FPGA-1-2-3: some of the lines DATA0-DATA15 are not connected to the board. :-(
About those monitors: I've been using two 1920x1200 (WUXGA) 23" monitors for 4 years now, my boss had to purchase them specifically for me when I was hired. They don't go into portrait mode but I solved the screen space problem by using 6 point fonts whenever I can. Those 4K monitors look nice but I don't think they would improve things a lot: the pixels simply get too small to use 6 point fonts so I won't get much more text on the screen than on those more-than-HD monitors without it becoming unreadable.
Tonight I finished testing the Prop2 Verilog. It's all complete, with the exception of the smart pin, which will get developed over the next month, with your help.
Tomorrow I'll get back on the documentation. At the moment, I've got a 12-cog image compiling for the Prop123-A7 board. It uses the 50MHz clock, directly, so there are no issues with PLL's.
Hopefully, I'll have a downloadable .zip with everything you need sometime in the next few days.
Tonight I finished testing the Prop2 Verilog. It's all complete, with the exception of the smart pin, which will get developed over the next month, with your help.
Tomorrow I'll get back on the documentation. At the moment, I've got a 12-cog image compiling for the Prop123-A7 board. It uses the 50MHz clock, directly, so there are no issues with PLL's.
Hopefully, I'll have a downloadable .zip with everything you need sometime in the next few days.
Sounds great! I'm looking forward to a DE2-115 image.
I get crickets every time I say this, but since we're looking at smart pins, here it goes again.
1. Very few applications use all I/O pins, therefore most of the time there are some left over.
2. Many measurement schemes lend themselves to a free-running oscillator design.
3. The ability to make 2 pins, adjacent ones perhaps, into an asynchronous inverter would facilitate this, and make the signal available to a counter without adding additional chips, traces, vias, bypassing, etc
In Prop1 I routinely make a counter into an inverter for these reasons. Of course, this is a synchronous inverter, but is often still accurate enough. Asynchronous would be perfect.
I got the full-memory downloader working tonight on the PNut.exe program. Up to this point, all my development had consisted of downloading 512-long loaders. Now we can start assembling much bigger code that can fill the 512KB hub RAM.
After that, I worked some more on the documentation that you guys will need to program the Prop2 using the FPGA boards. For those familiar with the previous Prop2 effort, these are the only things that you'd need to know about to program the new Prop2:
XFR
MEM (+LUT)
ALTDS
COG/LUT/HUB execution, PC behavior and branching instructions
events/interrupts/debug
CORDIC
COGINIT, now can indicate cog/lut/hub-exec
SETQ/SETQ2
REP
These are the things that require special explanation. It's not a long list, thankfully. Once smart pins are working, that will be another topic.
1. Very few applications use all I/O pins, therefore most of the time there are some left over.
For the P1 it seems to me that the biggest problem (at least the one I run into, with every board I'm using) is that there are never enough I/O pins. As soon as you start to attach RAM, for example.. before you know it you'll have to choose between VGA or something else because there are not enough pins to have it all. Of course, with the P2 there are more pins and the situation may be totally different. I have been waiting for those pins.
Comments
( A SMD poked under the corner seems a solution )
The -A9 actually has 16 fewer I/O pins. For this reason, the -A9 board will write to each video DAC on different edges of the clock. So, we saved pins by muxing the 3x10-bit data inputs to the DACs.
I need to get a BeMicro -A9 board to make configuration files for it.
I'll first make an image for the Prop123 -A7 board, which seven people have, already. Then, I'll do the DE2-115. Then, probably the DE0-Nano (1 cog) with the add-on board we had built earlier.
So far, OzPropDev has the only board that works straight up, vs 4 which don't, and a few more yet to know. Perhaps there are a few others in that batch of 30 that work straight up like OzPropDev's
It'd be great to get you, and others who made solid contributions to P2, involved earlier rather than later, if possible.
If its just 1 soldered resistor stopping you, then we have to help get that sorted. I'm happy to help where practical
Given Ken's A9 timing prediction, and assuming an A7 image is days rather than weeks away, it'll likely be mainly the A7 that helps flush out bugs and other usage issues. Its also possible we'll find further things that further delay the A9, once we get stuck into the A7.
regards
Lachlan
Mainly, though, my time was spent organizing the Verilog code to make it manageable and easy to look at. One thing that has helped a lot is having two 4k monitors turned 90-degrees into portrait mode. It's so much better to be able to see almost 200 lines of code at once, per monitor. It gives a whole new perspective on everything and makes it really easy to navigate. If you think about it, if you work through a peephole of 40 lines of code all the time, it is requisite that your brain maintains a mental image of the bigger picture. With 200 lines of code in your face, it's way less taxing on the mind.
You can see from line 729 the two 8-long programs that run on the cog to perform a cold start and coginit-induced start. On line 749 you can see where the instruction is picked from either the lut_q or the reg_qx (1st port of the dual-port cog ram), based on p[11], which is the program counter bit that crosses from $7FC (cog) to $800 (lut).
This business of making programs so that you can see more of them at once is really important. I've been thinking for years about how this can be done, besides increasing rows and columns. If we could make some kind of 2.5-dimensional representation, that might be a part of it. It would be neat if, at a glance, you could see your whole code - not necessarily legibly, but recognizably as a 2+dimensional shape that you could maybe spin into the desired perspective to edit it.
Totally. My one big coding project I've done I was given a textmode folding editor. I didn't think anything of it at the time but it didn't take long before I had created layers of folds, particularly for the GUI structures. The editor stored the folded state of each fold in the source ... not to mention features like multiple views of the same file. In hindsight, I now recognise how much the text editor mattered for development manageability when limited to just a single 40 line display.
Some card with two DisplayPort connectors. It wound up dictating a new motherboard. So, it was twice as expensive as we anticipated. After a bit, I went back to 1920x1080 resolution because it made everything easier to read, like the menu bars. Right now, though, I've gone back to 3840x2160 because I'm mainly looking at text. Portrait mode is really nice. I just didn't realize, at first.
Back in the day awe would print our source on that wide green ruled fanfold line printer paper. As long as you like. Then you get a good view of your creation.
This was in the mid-eighties. Got his code sorted out though (later I rewrote it to something smaller..)
-Tor
I did once manage to prune a function on 3 of those fanfold pages to just two lines. My colleague out did me he got it down to one line. We decided to go with my version as it was actually readable.
Maybe I'll buy a second one.
The Sublime editor has a "greeked" version of code on the right side for the purpose of seeing the whole thing as a rough shape.
Re: Si5351 breakout solution - that's a really nice I2C programmable clock chip. I've ordered the board and connectors but haven't found the cables yet. Being a programmable clock, it needs something to talk to so you can set it up and get it running. It looks like I may need to build a little "clock box" for my bench out of the breakout board and a spare Arduino (quickest solution since Adafruit has a sketch already).
I remember less than 20 years ago a 19" VGA 800x600 monitor (CRT of course) cost $2,500 wholesale.
Still have a couple of boxes of fanfold paper - only good for grandkids to draw on now
I'm on mobile and the link looks like it won't work. Search on asus display link screen.
I went through the BeMicro-A9 schematics and it looks like it's not possible to connect the Propeller to download the binary in the same way as on the FPGA-1-2-3: some of the lines DATA0-DATA15 are not connected to the board. :-(
Feel free to use my .qsf file at https://github.com/jacgoudsmit/P1V/blob/rel/HDL/BeMicroCV-A9.qsf (and I'm open for any improvements on that, too!).
About those monitors: I've been using two 1920x1200 (WUXGA) 23" monitors for 4 years now, my boss had to purchase them specifically for me when I was hired. They don't go into portrait mode but I solved the screen space problem by using 6 point fonts whenever I can. Those 4K monitors look nice but I don't think they would improve things a lot: the pixels simply get too small to use 6 point fonts so I won't get much more text on the screen than on those more-than-HD monitors without it becoming unreadable.
===Jac
Tomorrow I'll get back on the documentation. At the moment, I've got a 12-cog image compiling for the Prop123-A7 board. It uses the 50MHz clock, directly, so there are no issues with PLL's.
Hopefully, I'll have a downloadable .zip with everything you need sometime in the next few days.
Prop123-A7 board all "warmed up" and ready to go!
1. Very few applications use all I/O pins, therefore most of the time there are some left over.
2. Many measurement schemes lend themselves to a free-running oscillator design.
3. The ability to make 2 pins, adjacent ones perhaps, into an asynchronous inverter would facilitate this, and make the signal available to a counter without adding additional chips, traces, vias, bypassing, etc
In Prop1 I routinely make a counter into an inverter for these reasons. Of course, this is a synchronous inverter, but is often still accurate enough. Asynchronous would be perfect.
After that, I worked some more on the documentation that you guys will need to program the Prop2 using the FPGA boards. For those familiar with the previous Prop2 effort, these are the only things that you'd need to know about to program the new Prop2:
XFR
MEM (+LUT)
ALTDS
COG/LUT/HUB execution, PC behavior and branching instructions
events/interrupts/debug
CORDIC
COGINIT, now can indicate cog/lut/hub-exec
SETQ/SETQ2
REP
These are the things that require special explanation. It's not a long list, thankfully. Once smart pins are working, that will be another topic.
-Tor