Verilog versus VHDL, or maybe both
LoopyByteloose
Posts: 12,537
Rather than reading tutorials and then creating the project according to what I learned, this time I started out with the project defining what I need to learn. One does have to eventually step away from what others teach and think for one's self. It is empowering.
I decided to begin with the P1V verilog project and to attempt to replace the CPUs with an optimized Forth CPU. It seemed that Zen Forth and the eP16 were the best available, but it is all in VHDL and on a Lattice FPGA. So I am learning both Verilog and VHDL in parallel.
More specifically, I have actually decide to learn both Altera with Quartus II and Lattice with Diamond IDE, and Verilog and VHDL at the same it. This is not going to happen quickly (like in a weekend), but slogging along over the long haul has its rewards.
So far, I have got the P1V loaded and working on the BeMicroCV with Tachyon Forth or pfth Forth, so I have demonstated that the Verilog code works and I can opereate Quartus II V.15.0.2.xxx. And determined how to make modifications to the BeMicroCV and CVA9 that will enhance their usefulness
Verilog looks easier to learn, but I haven't gotten deeply into the P1V quite yet. I switched over to the eP16 code at this point. Zen Forth has long been something I wanted to get into. So I am now trying to get the Lattice Brevia2 XP2 loaded. And C. H. Ting's documents seem to demand I learn something about it along the way. It also may help me to eventually understand the P1V Verilog as that code stands alone without a lengthy presentation.
Now I am reading the eP16 documentation with intentions of getting the ZenForth working on a Lattice Brevia2 XP2 that I already purchased. The documentation from C.H.Ting is clear and very informative. I also have a VHDL Tutorial which includes a conventional 32bit CPU example.
I also have a PDF that compares Verilog and VHDL with examples. I keep returning to that to see what might be confusing me. So far, it seems to be very rewarding -- especially contrasting Verilog and VHDL. I must have learned something from Parallax over the years as it seems to be easier than I expected.
There are code converters - VHDL to Verilog, and Verilog to VHDL. I suspect the VHDL to Verilog direction might be safer to purse. But I can't see exploring these until I at least attempt to visualize do the changeover without automation.
And I am really enjoying what FPGA bring to the situation. I can have anything I want (within reason). I don't have to wait for the Propeller II to have more resources. And I don't have to look at a minefield of specifications for switching to another brand that may or may not be what I want.
In fact, I am beginning to think that learning Verilog and VHDL in parallel might be a better way to go.
I decided to begin with the P1V verilog project and to attempt to replace the CPUs with an optimized Forth CPU. It seemed that Zen Forth and the eP16 were the best available, but it is all in VHDL and on a Lattice FPGA. So I am learning both Verilog and VHDL in parallel.
More specifically, I have actually decide to learn both Altera with Quartus II and Lattice with Diamond IDE, and Verilog and VHDL at the same it. This is not going to happen quickly (like in a weekend), but slogging along over the long haul has its rewards.
So far, I have got the P1V loaded and working on the BeMicroCV with Tachyon Forth or pfth Forth, so I have demonstated that the Verilog code works and I can opereate Quartus II V.15.0.2.xxx. And determined how to make modifications to the BeMicroCV and CVA9 that will enhance their usefulness
Verilog looks easier to learn, but I haven't gotten deeply into the P1V quite yet. I switched over to the eP16 code at this point. Zen Forth has long been something I wanted to get into. So I am now trying to get the Lattice Brevia2 XP2 loaded. And C. H. Ting's documents seem to demand I learn something about it along the way. It also may help me to eventually understand the P1V Verilog as that code stands alone without a lengthy presentation.
Now I am reading the eP16 documentation with intentions of getting the ZenForth working on a Lattice Brevia2 XP2 that I already purchased. The documentation from C.H.Ting is clear and very informative. I also have a VHDL Tutorial which includes a conventional 32bit CPU example.
I also have a PDF that compares Verilog and VHDL with examples. I keep returning to that to see what might be confusing me. So far, it seems to be very rewarding -- especially contrasting Verilog and VHDL. I must have learned something from Parallax over the years as it seems to be easier than I expected.
There are code converters - VHDL to Verilog, and Verilog to VHDL. I suspect the VHDL to Verilog direction might be safer to purse. But I can't see exploring these until I at least attempt to visualize do the changeover without automation.
And I am really enjoying what FPGA bring to the situation. I can have anything I want (within reason). I don't have to wait for the Propeller II to have more resources. And I don't have to look at a minefield of specifications for switching to another brand that may or may not be what I want.
In fact, I am beginning to think that learning Verilog and VHDL in parallel might be a better way to go.
Comments
This site mentioned above might be of interest. The DE0-Nano seems to be a good value with support from Parallax. At this point, I don't have one - but that doesn't mean much.
My initial investment in FPGAs included the folllowing:
BeScope
BeMicroCV
BeMicroCVA9
Lattice Brevia2 XP2
And I am including a PDF of a Verilog/VHDL comparison. It may not be the best out there, but it is what I have been studying.
The other two PDFs make up my current bookshelf. I will stick with them until an obvious need to go to something else arises.
The reasons for buying what I have and using the documents I do are not entirely rational.
https://www.joelw.id.au/FPGA/CheapFPGADevelopmentBoards
I am somewhat curious on what i might have missed out on.
I can't help but think you are piling complication upon complication for yourself.
Did you say elsewhere that "Small spaces concentrate the mind" or some such?
I would pick one language, VHDL or Verilog. One dev board. Figure out how to work in that space.
For example, have you gotten so far yet as to write your HDL that can flash a LED or perhaps respond to a switch input? The "Hello World" of any dev system.
I guess I seem to be contradicting myself to some. But I feel there is nothing wrong with big projects in small spaces. I am still dealing with relatively small CPUs and limited RAM resources. Also, I am avoiding anything remotely near to a GUI or a file system.
These FPGA devices indeed can get into much larger projects than I am use to. But I am no longer a rank beginner. I need to move on. I just feel that begineers need the discipline of smallness to suffer less confusions and distraction. For instance, one can learn digital maths clearly with just 4 bits; using 8, 16, 32 or more tends to distract with more ones and zeros -- but have the same problems with sign and carry bits.
But essentially I have a plan and been following it.
A. Get the P1V working on the BeMicroCV and load Tachyon and pfth Forth on it
B. Get the eP16 working according to C. H. Ting's prefereences -- use the LatticeXP2 Brevia2 and verify.
C. Migrate the eP16 VHDL to working on the BeMicroCV, which requires at least adapation of the memory.VHD module.
D. Attempt to convert the eP VHDL to Verilog, compile and run
E. Attempt to create an 8 Cog eForth CPU.
This may take quite awhile, but I do have the time. My main reasons for sharing are because I still feel the Propeller 1 is the best Forth platform currently available and I am wondering if this might be an improvement upon that.
If I was a bit smarter or not so new to FPGAs, I suspect I could just read the documents and adapt the Lattice XP2 Brevia2 directly to the BeMicroCV. But it was relatively inexpensive to buy the board and begin with just loading what has been achieved.
Ok, call me different but I completely bypass the books. I skip the tutorials, and I ignore all the online education. I start with a complete emulation of a computer and build my knowledge from there. For the propeller, that was a Z80 computer - heater's idea, which evolved into a working machine by pullmoll. For FPGAs, it is Grant Searle's website doing something similar.
For me, I want to see working stuff! For example, give me a uart. It can be a chip with pins and you hook it up on a breadboard. Or some pasm running in a cog on a propeller. Or some vhdl code. Feed in a byte in parallel, out it comes in serial. Now let's pull it to bits and see how it works.
I know enough about FPGAs to be dangerous
I dunno, sometimes you have to just try stuff. I put Grant's Z80 machine into the Cyclone II he recommended and got it working. Then tried adding bits and ran out of memory. Then got on ebay searching for cheap FPGA chips, looking for that sweet spot of price vs performance. I think it is Cyclone IV rather than Cyclone V but I could be wrong there.
Then jump right in and port a cyclone II design to a cyclone IV chip. Writeup here http://www.smarthome.jigsy.com/fpga
Still pulling it to bits and tinkering. I like the general idea with VHDL that you design a "component" - it sits in a directory, it is a single vhdl file that you can edit with a text editor, it has inputs and it has outputs. It is very similar to a physical chip. Then in the 'main' program, you plug these components together. There is piles of code describing how things connect, which the compiler strips down to simple joins between things. A uart - well it has an 8 bit bus, control lines, and input and output pins. The data bus joins to the CPU. The serial bits - well they get joined to physical pins on the chip, and there is another file for those joins.
I have this crazy idea of hybridising a Z80 chip and a propeller cog all on one FPGA design. Why not? Why not hybridise several CPUs together? So many fun things to do!
Not sure how many LEs a cog takes. 2k of ram internal, dunno, maybe as complex as a Z80 chip, might be a bit simpler, maybe more an 8080? Just guessing there.
And there are some cool things FPGAs can do that the prop and the Z80 can't, like dedicated multiply cores. I had some fun creating multiple 8 bit output ports, multiplying the numbers together and reading back the answer. A co-processor in a few lines of VHDL.
But don't read the manuals. Who reads those anyway. When I was 8 my dad bought a brand new hot water service, and it came in a very complicated wooden box that my dad spent half a day trying to open. And when he got it open, inside was the instruction manual for opening the box. And it started with words I can still hear my dad reading in disbelief "We realise by now you will have opened the box, but we have included this instruction manual so you will know how to open the box if you ever buy another of our fine hot water services"
Have fun with vhdl and verilog!
It did lack a couple of instructions that are not used by those systems. One day I might get around to fixing that but the whole project has been on hold waiting for a P 2 so that we don't have to mess with external RAM. Of course the impetus to do that has evaporated because we can now make a Z80/ CP/M system on a tiny a 2 dollar STM32F4. (Except of course the video for the terminal display will be easier on a P2)
Pullmoll's Z80 implementation is indeed an improvement, 100% instruction accuracy together with more hardware supported in emulation.
Where is PullMoll? Those were fun times as we were both trying to perfect Z80 instruction emulation at the same time.
For me, the BeMicroCV at $49.00USD including SDcard slot and other features seems equal in value to just about any $50 Propeller board. Just replace the 24C01 I2C EEprom with at least a 32Kbyte one and you have lots of new resources that you maybe have been waiting for -- more i/o pins, attachment of Analog Devices ADC boards, larger hubram, and so on.
But it all requires one to at least learn Verilog.
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I am all for empowering actually learning as opposed to merely surfing and shopping the internet for amusement. Much of the stuff about microcontrollers is rather superficial and distracting to me. I have no desire to interface 37 Arduino gadgets or to replicate another BOEbot.
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I have laid out a study plan that I am following. It is certainly not a beginner's course in CPU architecture. It is more of a first course in FPGA deployment of CPU designs.
So far, Dr. C. H. Ting has been very helpful in offering tips on how to avoid over-the-top complexity in VHDL that one might get into by just reading a VHDL or Verilog textbook. I am mainly attracted to him because he has always been passionate about 'the simplest approach is the best'.
While the Z-80 certainly has its place in history, CPU architecture has evolved since then. But I can certainly understand emulation of it as a means to contrast what one has mastered with what one is now learning. IN this case, both Dr. Acula and Heater used it to gain a deeper understanding of the Propeller. (I never mastered the Z-80, the 6502, the 68000, and so on.)
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Where am I now?
Shamefully, I am in Windows 7 starter as the Diamond IDE was installed in it while I was fooling around with cleaning up my dual boot configurations.
And I am now trying to actually work out a first attempt to compile and load the eP16 image to the Lattice XP2 Brevia2. If that goes well, I will immediately move on to using the same VHDL in Quartus II v.15.0.2.xxx on my BeMicroCV which is loading in Linux. So I won't be in Windows 7 long.
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There was a second reason for the Windows 7.
Dr. C. H. Ting provides a eP16 emulator that works on in Windows, no Linux support.
So I was able to boot that and confirm it really is working. This may become a needed support item in the future.
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So that's all the discussion for now. I need to stay with what I am doing. Of course, I should always be doing something else -- like filing my 2014 Income Tax that are on an extended deadline.
But fun always feels best when being a bit naughty.
I stand corrected. And yes, they were fun times.
Back then in 2009 it was getting a Z80 running on a propeller emulation. Now it is getting a propeller emulation running on a FPGA. Still fun times!
This one uses a USB cable to program. It is NOT the Lattice XP2 Brevia which required a serial cable and parallel cable to program -- thank Heavens!
I provided a link in the above comment to an Aussie that has lists all the currently cheap FPGA dev boards. He missed that one, but is a great resource to help one get their first FPGA.
I only wish that Parallax was in a position to offer more of these bargain FPGA boards. After all they are providing the Verilog for free.
Oh yeah. FPGA->Propeller->Z80->CP/M
It's Turtles all the way down. As they say.
Sadly I don't have the time or mental bandwidth to get into the FPGA thing. Too many toys to play with now a days. Then I get paid to play with other toys....
I hit a snag when I found Windows7 demanding my Admin password to open the port to program the thing. In my recent clean-up of W7, I added a secure password that I didn't write down.
A few hours later it came to me, but I am too weary to continue tonight.
I did load PuTTY into Windows7 as a free terminal application which will be required. I am still digging through the eP16 documentation to determine if I can actually use the USB to the LatticeXP2 Brevia2 port or in I must wire up a USB to RS232ttl device for my Terminal interface.
So I had to download the actual development board schematic and pin outs to confirm where the Tx and Rx are signed in the eP16 code.
Time for a break. A good night's rest will do wonders.
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Heater,
If you don't want to play with FPGAs, the negativity isn't really informative.
FPGAs certainly tend to be lower level stuff... architectural choices within the CPU rather than a whole OS with applications, which you seem to prefer. But I am learning something and trying to share info that might make it more fun for others.
So far, the eP16 might actually be a much simpler architecture than a conventional CPU. And that is much of how it gains excellent speed. It will eventually be interesting to see if it can actually replace the Propeller Cog CPU with good results.
This example is 16 bits, so the eP16 will have to become an eP32 == which I do have some info on -- before it will be really ready to attempt to be combined into an 8 CPU scheme.
I REALLY LOVE reading about peoples projects, problems and ultimate solutions and being a newish prop and oldish Z80 fan, I would enjoy going over the posts describing this work, as I have for instance over the colour lcd project by Dr_Acula and others.
However looking at that hackaday site I see a parallax link for the work involved in that project
http://forums.parallax.com/forums/default.aspx?f=25&m=405722&p=1
that gives the following
Page Not Found
The page you were looking for could not be found.
Is there a new link for this or is it lost forever???
Dave
On the contrary I think the whole idea is great. Wish I had the time to pursue it. I don't get the idea there. A CPU and it's architecture is one level of abstraction, an OS and it's applications, or any software running on a CPU, is another level of abstraction.
Where did I say anything about which one I prefer to think about?
As it happens I'm interested in the whole stack. From the physics required to build the transistors, to the ways you can make logic gates, to ways you can arrange those into a processor, to the instruction sets and architectures, to the compilers and languages you can use with that, to the applications and operating systems, to the ways you can network all of that.
Sadly, I have a small brain and little time, so I can only actually play in a tiny part of that.
As I sit at my laptop in Ohio running a Linux distro which hosts a VM which is running Windows to run a VMWare thin client to connect to a virtual windows desktop that is running on virtualized server in Michigan that (I think) is running on real hardware, If I go full screen mode, it's very hard to tell I am not running windows directly on my laptop for most tasks. Come to think of it, my employer has some 60K+ servers...I have yet to actually see one in the past 10 years or so!!
It's an amazing world of turtles and the FPGA is just another fun layer of abstraction open for us to play in.
But I have been a bit bored with waiting for the Propeller 2 and gotten a bit negative without the help of others. I was waiting for Tachyon and pfth on the Propeller 2.
My impression is that Heater would much rather be working with Javascript than an FPGA. And Javascript is something I just rather not touch. Programmable silicon is more tangible to me than VM. Abstract layers? I am a bit wary of too much abstraction.
I am just doing my own thing with eForth to see if it can happen.
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Something is very wrong in how much of the old Parallax Forums cannot be found and may have been lost.
It people did something unique and did save their own work, a gitHub repository might be a wonderful way to preserve such work. There was a time when there were lots of website and such, but most seemed to have gotten busy with something else and just let go of the info.
IMHO Parallax would prosper by offering gifts and discounts to gitHUB maintainers.
Sorry if what I said sounded like "abandoning this whole scheme as just too ambitious". I did not mean that. Rather, as you said "small spaces focus the mind". That is, master one small space. Then look to making the space bigger. I'm with you there. Sad to say it may be too late now. I may never regain the enthusiasm for the idea now that there is so much else going on in the world of technology we can all play with.
Javascript vs FPGA? No, they are different things, at different layers of a tower of abstraction.
I happen to think that JS is rather magical thing. If nothing else it is the first programming language that every human being on this planet can use, given they have access to a normal machine by today's standards, out of the box, for free, with no strings attached.
Of course JS, as a language, in itself has other attractive and unique properties. See "The Official Javascript language war" thread.
FPGA is of course a road to building a machine that can be used to run JS
I agree with the sentiment "I am a bit wary of too much abstraction." I worry when finding myself using abstractions when I have no idea what it is they are actually abstracting! As of today, the forum search uses Google search. Which you could have used anyway by going to google. A quick test shows that stuff I wrote in 2008 is easily found.
I agree about the github thing. For a long time now myself and others have suggested that things like OBEX and users projects here would be better served by being maintained in a proper source code repository.
But over the long haul, a series of milestones in learning provide comfort. Continuity is important to remain engaged. And I see that all the so-called educational leaders in microcontrollers/microcomputers, they arelacking in continuity, including Parallax (I won't mention the other obvious ones). Just the jump from the BasicStamp2 to the Propeller is all too larger and daunting.
And then, there is the topic of actually learning how to achieve things on one's own via Project Management, evaluation of what is feasible, and setting a goal to seek answers the to unknown. All that is yet another level of education -- maybe a more important life skill today that any particular focus on electronics or programing.
This is a 'back-burner' project scheme. And it may just be of more value teaching one to enjoy living with the journey that a big project creates than to just go all out for an immediate result.
Frankly, I did finally learn project management in the real world, but I wish I had acquired the skill set much earlier as it makes success more possible and achievement more pleasant.
It is never to late to learn, but some things are really helpful to be learned earlier in life.
Above I may have mentioned that I had doubts about the BeMicroCVA9 working with the BeScope board. This is not directly related to this project.
But the BeScope may be used with either the BeMicroCV or BeMicroCVA9. I provided greater detail in the LVDA versus SPI thread.
Wish you well on this project. I can understand the steps needed to learn this. I put my CV away till I have time to study.
@Heater I have played with JS on a Beagle Bone Black. It is interesting and fairly fast. Its another tool!
A. The Lattice XP2 Brevia2 uses a 50Mhz oscillator, so something different in the BeMicroCV will actually clock the CPU
B. The Lattice XP2 Brevia2 memory solution for RAM is a 'black box' solution that only works on the its product, so the whole memory.VHDL needs a complete replacement on the BeMicroCV.
C. Pin outs will be different, but the BeMicroCV has more than enough to provide for such
D. Instead of working through the on-board USB to provide a serial terminal, I may have the USART ttl Tx and Rx connect with a USB to RS232ttl device. This might be the only way to deploy the serial interface, or it just may be easier than trying to exploit the BeMicroCV USB port with all its complexities.
I think that is a complete To Do List, so some bright person might actuall get eP16 loaded and running on a BeMicroCV before I do.
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Having achieved that eliminates the need to buy the Lattice XP2 Brevia2 or to bother learning the Diamond IDE.
At this juncture the whole project shifts to study and comparison of the Forth CPU in VHDL and the P1V in Verilog. And the next logical step would be to either migrate the eP16 to Verilog, and then adapt it to be an eP32 device (need the 32 bits for the Proeller right), or to modify the ep16 to be an eP32 in VHDL, and then change it all to operate in Verilog.
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I am still a bit unclear how that first Forth dictionary gets loaded, but I am presuming that the file sits on ones PC and is sent to the FPGA that has enough low level code to load the first time dictionary. C. H. Ting's discussion of the the Metacompiler is rather lenghty and academic. It offer more than a mere HOWTO. There are a series of <name>.f files that I have not yet figured their importance.
That may become very important for getting the default baud rate of 115,200 8N1.
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Right now I am working in Lattice DIAMOND IDE and Windows7 on the Lattice XP2 Brevia2.
I may simply go to a parallel effort to get the eP16 VHDL code to work on the BeMicroCV as this is not going well. And it obvious that the barrier is mostly learning the Lattice way with some Windows annoyances.
So far, the usually Windows follies..
I have to reboot three times to get past failing update installs before I can get to work, and then I ran into several security challenges to open my USB port to programing the device.
I am hitting a few other snags while trying to closely follow C. H. Ting's pdf... not sure why. It seems he desires me to generate a fresh ram_memory.vhdl file and I figured that the one provided is good. Diamond IDE won't seem to let me designate the right device -- the Lattice XP2.
I had tried just bypassing some steps, but that seems to not be working as I have yet to get to where I should designate the I/o pin assignments before loading into the device.
C. H. Ting's VHDL code seems to compile quite nicely. And while I don't quite understand why, you have to generate a ram_memory.vhd file even though one is provided. It may be that I neglected to include the mem.mif file in the project directory == but I wasn't told to do so.
But learning what all those Error and Warning messages mean in any FPGA development software is daunting. By starting with a Lattice product and then migrating to an Altera product, I double the workload. (I do admit I wanted to do so.) Others need not bother.
Where am I?
I am still in Diamond IDE for Lattice, and it seems that I compile the whole scheme and actually have successfully loaded something to the FPGA, but it won't run.
There is a file called a .ldf file - which I presume is a Load Designation File. C. H. Ting has typos that refer to it as .pdf file. The care and feeding of this file is central to get your i/o connected to the real world.
This wasn't my only problem. I had other configuration details wrong and had to start over with opening a new project. I may open a third new project tomorrow and see if that helps. There just seems to come a point where a project is damaged and beyond repair. So when all else fails, start a new one with your new bright knowledge.
Still at this point, I strongly suspect the clocking assignments in the .ldf file are just wrong. The i/o pin designations all look good (they should as I had to type them all in myself, no way to auto-generate).
Another wrong place might be the actual eP16_chip.vhd files ram memory section.
When I generated the new ram_memory.vhd, I was unable to locate a ram_memory_template.vhd file to cut and paste into the eP16_chip.vhd. Not sure if C. H. Ting got his procedure wrong or if Diamond IDE eliminated the step. I must research provided documents.
What do I think is next?
Getting the Lattice XP2 Brevia2 in Diamond has been a good introduction to what C. H. Ting intended and to eP16, but it also doesn't have to be done. If I were to simply get eP16 VHDL code working in Quartus II and on the BeMicroCV -- that is where the real migration of VHDL to Verilog code begins.
I hope I am not boring people with this rather long slow preamble.
I might as well start an attempt to use the VHDL files in Quartus II for a BeMicroCV, even if I don't get the Lattice device working. Having already gotten the P1V operating in Quartus II on the BeMicroCV means that I might actually achieve that sooner than figuring out what C. H. Ting and Lattice desire.
Another big plus is that I would go back to just using my Linux and not have to deal with some quirks of W7 that I never learned.
Lattice and Diamond IDE have gotten me completely confused.
So I will switch over to just the creation adapted the eP16.vhdl files in Quartus II V15.0.2 for the BeMicroCV. Ram_memory.vhd will have to have a complete replacement created specifically for Altera
Why quit now?
Well, I have successfully programed P1V on the BeMicroCV... and the Lattice XP2 Brevia2 just seems to accept my code and refuse to run. I can't sort out if I missed something procedurally in the Diamond IDE or what. Tutorial documents from Lattice don't specifically support the Lattice XP2 Brevia2, so by the time I might have run down 'this and that' in Lattice, I might find a good working solution already on the BeMicroCV.
(Plus I might learn from Quartus II, what I don't understand about Diamond IDE.)
Since nobody here is using Lattice, at least a Quartus II problem would be more interesting. And there is the possibility that I have found all the errors and omissions that might remotely apply in the eP16 VHDL code. So the Lattice XP2 Brevia2 can't just wait.
I am beginning to think there are at least three problems with the eP16 VHDL code.
One might consider them bugs, or they might just have been left to challenge anyone that desire to use the code to really understand it.
The regeneration of the ram_memory.vhdl is the first one and most obvious.
Then there seems to be an issue with CTS in the UART code and a couple of other i/o lines that are left loose.
Finally, one line in the eP16.vhd file itself is not right. That requires one to read the code for the CPU critically with an eye toward what it is supposed to do. This will require some effort to learn VHDL syntax in depth.
All three of these problems will turn up in either Lattice or Altera. I am just consdering them homework. I did have the Simulator running in Lattice Diamond IDE today, but the above prevented it from showing signs of life. The UART output is suppose to immediate emit a <CR> and <LF> if everything is right.
Still pushing to abandon Lattice and address the rest of the project in Quartus II, but re-reading the documents by C.H.Ting drew me back into Lattice.
You can mix VHDL and Verilog in the sense that some modules can be VHDL and some Verilog in the same project. No need (unless you want) to convert them
Edit: I use Lattice's Diamond and like it more than Quartus
Yes, that is the same Pullmoll that created the qz80 Z80 emulator for the Propeller and the Z80 emulations for MAME.
Although I got the idea that MAME no longer uses his Z80 emulator for some strange reason.
Pullmoll is a genius. After I created the ZiCog Z80 emulator for the Propeller he turned up here to create his own. He tried all kinds of different ways to optimize the emulation, starting with translating Z80 opcodes to PASM on the fly as I remember.
After what seemed like trying a dozen different approaches he hit a working solution. He was coding like a demon.
Pullmoll knows his Z80!
Where is Pullmoll?
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I finally gave up on Lattice Diamond IDE in Windows 7 Starter.... after a weekend of odd Windows update behavior and Diamond IDE seeming to get lost why the Windows 7 was complaining that the hard disk partition was nearly full. Menus that were once available in Lattice were shut down.
Not sure why.....
Removing Lattice Diamond IDE made Windows 7 Starter calm down.
So I moved over the Quartus II in Debian and attempted to restart the eP16 VHDL files. The first few steps were very routine.
But after locating a Dual Ram Memory in the Altera IP Cores menus, I am finding the software locks up before I can even configure a ram module. One of my Quad CPUs just jumps to running 100% and that application become as zombie. That process is taking 25% of the computer's resources in a runaway mode.
What to do?
First read the Altera IP Cores Manual... duh?
Then if no luck, I might consider adding another boot (making a triple boot out of the 64bit Quad) to allow for Red Hat/Fedora Linux. Then reinstall Quartus II in the Linux which Altera prefers.
Both Altera's Quartus II and Lattice's Diamond IDE seem to prefer that side of Linux.
I have plenty of space to partition for another Linux, and it might just be easier than wondering if that is the problem.
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So the good news is...
A. Yes there is a way to generate an appropriate two port ram_memory.vhdl for eP16 in Quartus II via Altera IP Cores. But I am just finding it broken. Not sure what the repair will take.
B. And I think that I can either assign a weak pull in VHDL to solve the CTS float problem, or just loop it to RTS. I would prefer the first and possibly provided the RTS and CTS as actively available to the outside world. It seems that they were left unresolved in the UART module.
The other two loose ends in the wiring assignments have yet to be run down. The seem to be involved in acknowledging interrupts. (Yes, eP16 provides 5 interrupts to the outside world. I am not sure why, but it does.) These may be unrelated internal interupts, or somehow connected to the outside world interrupt scheme.
C. And the pesky item in the CPU is still eluding me.
I am suspecting an END IF might be included where only an END is required. But I can't be sure without reading about VHDL syntax and thinking carefully about the flow of what is going on.
My EEEpc with Windows 7 Starter has been running clean up scans all day today. Remove unneeded files, defragment the partition, Windows security scan, A/V scan, update scan, registery scan and so on. Lovely LInux doesn't have me doing all this. It the system is corrupted, one just reinstalls and moves on.