Some very interesting work is being done (refreshed) in Europe
Mostly thanks to the regularity of the RISC instruction set, the size of the compiler could be reduced significantly.
It now measures less than 2900 lines of program and compiles itself in about 3 seconds, which is proof of its efficiency.
The entire system compiles itself in less than 10 seconds.
Considered extravagant and hardly necessary only years ago, run-time checks are generated automatically. In particular, they cover index range checks and access to NIL-pointers. Due to their efficiency they hardly affect run-time speed, but are a great benefit to programmers.
bold added, and I think those build time numbers are for a modest 25Mhz CPU clock !
Some porting is already underway - example
A screenshot is here ( I think @ 1024 x 768, VGA, 75MHz Pixel Clock, 25Mhz CPU clock )
More forum comments here
The FPGA host has 1MB of RAM (32b), (+SD) which is rather close to planned P2 resource of 512k, and I cannot yet find mention of how much of that 1MB was actually needed for the builds above, or the final 'EXE/BIN' sizes.
Present core used is FPGA 32b Soft-CPU RISC5
(not to be confused with RISC-V), but this bit from above .PDF gives other pathways :
A welcome consequence of the simplifications of language and processor is the fact that all parts that had been written in assembler code in 1992 -- and therefore were not included in the book -- have now been expressed in Oberon as well
That comment makes it look like porting to P2 involves just the back-end of the compiler. (which would be compiled on a PC host, before being able to self-compile inside P2 )
Source of Compilers and RISC5 (in verilog) are here
I think this is the RISC5 binary code-generator portion
date stamped quite recently
[" NW 31.5.2015 code generator in Oberon-07 for RISC Code generator for Oberon compiler for RISC processor."]
and the binary-opcode building is done in Put0 thru Put3
It seems the original PCB had 32b memory, and the porting above added an external 32b RAM for simplicity of least changes, but the now-accessible Cyclone A9 device can give 1MB in the FPGA.
I'll continue looking for Binary image sizes, and actual Build memory requirements.
The total system includes
17. The Processor's Environment
17.1. The SRAM memory
17.2. Peripheral Interfaces
17.2.1. The PS-2 interface
17.2.2. The SPI interface
17.2.3. The RS-232 interface
17.2.4. The display controller
17.2.5. The Mouse interface
The simple Verilog modules for each of those low-level peripherals, would re-map to P2 COG(s)