What's the Latest with the Smart Pin Development? Is It the Next Big Push?
JRetSapDoog
Posts: 954
It looks like the Prop 2 is shaping up nicely based on Chip's recent comments in other threads. HUBEX is done and he's nearly finished with an efficient but flexible interrupt scheme (new territory for the Propeller, not the "dark side"). There's still work to do, of course, but it looks like we're picking up speed. One (maybe the only) big thing remaining is the smart pins. I wonder how that part of the design is shaping up (I forget to what extent, if any, Treehouse will be involved in that).
I sometimes wonder to what extent Parallax has internal timeframes in mind for passing various mile markers, or a sense-of-urgency for completing the chip. I know it's a top priority and I think Parallax has a sense-of-urgency about doing it right and on their own terms. And I know and am glad that Chip works in an environment where he has the freedom to innovate further on the design, such as the interrupt mechanism just mentioned.
Anyway, the following article about some new offerings from Microchip reminds me a bit of the Smart Pins (Yeah, I once called them Pin Heads and thought that the name could foster some great cartoon illustrations, at least back in the more playful Parallax days). Here's an excerpt from the article:
"Microchip announces two new 8-bit families that expand its growing portfolio of innovative PIC® MCUs with Core-Independent Peripherals (CIPs). 8-bit MCUs can now be used in a much broader range of applications, due to the growing number of these intelligent, interconnected CIPs that combine to perform functions autonomously, without the core. Because these functions are deterministically and reliably performed in hardware instead of software, CIPs enable system performance that is far beyond typical 8-bit MCUs while simplifying the design experience and reducing memory cost. "
And another: "They are the first MCUs to integrate an ADC with computation, which performs input and sensor interface functions such as accumulation, averaging and low-pass filter calculations in hardware instead of software, enabling the CPU to Sleep or execute other tasks"
Link: http://www.eedesignit.com/8-bit-mcus-feature-core-independent-peripherals/
For me, the P2 is shaping up to be just about the perfect chip for my needs, so I have no plans to jump ship, and I think that would be jumping into a somewhat different kind of ship, at that. Anyway, I'm just passing this info along as general interest. I'll confess that my main plans for the P2 don't really involve most of what the smart pins will be capable of (some, though), but I'm still glad they will have those smarts. If Parallax had the resources to do more than one chip and a P2 with smart pins were still a ways off, I might slightly push for a digital-only version again. But I don't think that's in the cards (and Chip is heavily into analog, real-world stuff, and rightfully so). So, I'll gladly take a chip that has more functionality than I might use in one design. Cheers!
I sometimes wonder to what extent Parallax has internal timeframes in mind for passing various mile markers, or a sense-of-urgency for completing the chip. I know it's a top priority and I think Parallax has a sense-of-urgency about doing it right and on their own terms. And I know and am glad that Chip works in an environment where he has the freedom to innovate further on the design, such as the interrupt mechanism just mentioned.
Anyway, the following article about some new offerings from Microchip reminds me a bit of the Smart Pins (Yeah, I once called them Pin Heads and thought that the name could foster some great cartoon illustrations, at least back in the more playful Parallax days). Here's an excerpt from the article:
"Microchip announces two new 8-bit families that expand its growing portfolio of innovative PIC® MCUs with Core-Independent Peripherals (CIPs). 8-bit MCUs can now be used in a much broader range of applications, due to the growing number of these intelligent, interconnected CIPs that combine to perform functions autonomously, without the core. Because these functions are deterministically and reliably performed in hardware instead of software, CIPs enable system performance that is far beyond typical 8-bit MCUs while simplifying the design experience and reducing memory cost. "
And another: "They are the first MCUs to integrate an ADC with computation, which performs input and sensor interface functions such as accumulation, averaging and low-pass filter calculations in hardware instead of software, enabling the CPU to Sleep or execute other tasks"
Link: http://www.eedesignit.com/8-bit-mcus-feature-core-independent-peripherals/
For me, the P2 is shaping up to be just about the perfect chip for my needs, so I have no plans to jump ship, and I think that would be jumping into a somewhat different kind of ship, at that. Anyway, I'm just passing this info along as general interest. I'll confess that my main plans for the P2 don't really involve most of what the smart pins will be capable of (some, though), but I'm still glad they will have those smarts. If Parallax had the resources to do more than one chip and a P2 with smart pins were still a ways off, I might slightly push for a digital-only version again. But I don't think that's in the cards (and Chip is heavily into analog, real-world stuff, and rightfully so). So, I'll gladly take a chip that has more functionality than I might use in one design. Cheers!
Comments
Click on the top right hand 'Options' star on your posts and edit should appear, no idea why it hidden like that.
Quotes are always a lottery, especially nested quotes., you can go into HTML mode (right most button on tool bar [<>] and then manually strip out the fluff..
If Parallax had the resources to do more than one chip and a P2 with smart pins were still a ways off, I might slightly push for a digital-only version again. But I don't think that's in the cards
The smart pins now contain the counters, so a P2 without smart pins, is never going to go to silicon.
(and Parallax do not have the resource for more than 1 chip)
There will be plenty to test on the P2 prelim release FPGA image, before smart pins are fully done.
Regarding smart pins, no, I definitely want smart pins and do recall that the counters have been moved there. In fact, based on the last that I read/recall, there will be no redundant P1-style counters in the cogs (for P1 compatibility or whatever). But what I meant to say was an all-digital version of the chip (without the analog features of A/D or D/A), though I do have a definite need for the D/A functionality. Anyway, that was just a passing comment, and I look forward to the smart pins. Thanks for your help again, as well as your comments.
When I had this crazy idea...
What if the smart pins were implemented as a tiny 4bit fast little cousin per pin?
Now, I am not at all sure how this might work, but it could be quite functional.
BTW I still am not sure what the smart pins are going to be capable of.
Guess we need to get some info from Chip and I cannot wait for that
When I had this crazy idea...
What if the smart pins were implemented as a tiny 4bit fast little cousin per pin?
If you can code that in 180nm, and get it to count and capture 32 bits at SysCLK speeds, sure!!
I have seen tiny state engines and CPLD like structures done around main peripheral hardware, mainly to control start/stop rather than to pump the actual data.
Microchip claim smart peripherals that can report Frequency and Duty Cycle with little CPU intervention.
I presume they mean the actual capture side of things, proper frequency reading needs a reciprocal calculation of a dual capture of Cycles and Time & proper Duty cycle needs dual capture of Period and Gated-Time..
The calculation is unlikely to ever locate in a peripheral, but the dual capture of Cycles and Time should be well wihtin the smart pin realm.
Chip has just indicated that if the final silicon gets tight on space then some of the pins could end up being plain digital I/O only.
He's talking about the design of them, and that he wants our use cases and input on what might get those done optimally.
Start thinking small and brutal.
Hey, on that 4bit CPU idea, would the gist be to just shoot a little bit of code over to the pin? So the smart pins could technically get smarter over time? Or maybe they can perform a lot of functions, but not all at the same time.
Given the potential crunch for space, maybe that's worth a thought. We could then have another little assembly language for them. Pin-objects.
I will just wait for Chip to be ready. However the smart pins might be able to some of the job so I would like to see how that's going to pan out too.
At one point in the main thread, Chip said, "Cluso, I should probably start understanding what we need for 12MBPS USB CRC'ing."
The smart pins need counters for existing P1 modes, need to be able to operate in pairs, and do in/out serially, plus of course the analog mode.
So we could have 16 x 32bit cores and 64 x 4bit cores
400MHz would be very unlikely, and I'd need to see some compelling use cases.
The COGS are 32 bit and the counters will read/capture/shift to 32b sizes, so a 4b MCU is going to take 8 cycles just to read any 32b value.
Cypress started their PSoC series with minimal peripherals and a 'Roll it in Logic' philosophy, but their newest ones have dedicated peripherals, and still have some Logic, but not wasted doing things like counting or shifting.
It's not necessary for the 4bit cpu to read a full 32 bits at once. It just requires a 32 bit register that it can rotate in an instruction and potentially set a flag or do something depending on the result of a resultant bit. It could be just a shift out to a pin(s) instruction.
So the tiny cpu would have a few specific dedicated instructions. Certainly it would not be a general purpose cpu.
About your 4-bit "pin-processing units" (PPU's), I was just going to ask if they would have their own memory or continuously receive instructions from a cog, but I see that you've mentioned their "tiny memories" above. What's the typical instruction size for a four-bitter? I suppose it's between 4 and 8 bits, though 4 bits wouldn't allow for many instructions. Anyway, Chip considered 32 cogs at one time. If there were definite use cases and silicon real estate for PPU's, I'm sure he'd consider it.
Love your "PPU's" acronym
I was just thinking of some tiny processor or state machine that could be programmable. Perhaps 256x4 ram might be plenty. Chip will know the basics of what little instructions would be required. If we can load the ram imagine the uses everyone would experiment with. We could have as much fun with the PPUs as we had with P1
There is no point using fixed hardware if we could use something generically programmable providing it doesn't use much silicon.
So the tiny cpu would have a few specific dedicated instructions. Certainly it would not be a general purpose cpu.
So they are not data-path engines, more state-engines with some flexibility.
I think I've seen MCUs with user accessible state engines around flags, for things like COMs handshakes etc.
... Find this wording from Infineon
["programmable peripheral control processor (PCP) engine"]
Then there was the TPU from Motorola, which has morphed to this eTPU on new Freescale parts
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=eTPU
["
- Up to 64K bytes of code memory and 4K bytes data memory (actual amount implemented varies by product)
- Flexible allocation of data memory per function" ]
& there is a similar sounding xgate on the S12Xhttps://en.wikipedia.org/wiki/Freescale_68HC12#XGATE
I like CRAVE the idea of some very simple CPLD-like functionality at the pin level. What couldn't you do with a simple NAND-NOR between adjacent pins? Especially if it's non-synchronous. I'm usually measuring something, and gravitate toward measuring resistance, capacitance or inductance with a free-running oscillator. Therefore just having something as simple as a selectable non-synchronous inverter available between pins would save on the BOM, use up those unused pins, and makes the result immediately available for counting or timing.