P1V working on BeMicroCV-A9
jac_goudsmit
Posts: 418
I'm happy to report that I got the P1V (Verilog version of the Propeller) working on the BeMicroCV-A9. Check out my Github repository at https://github.com/JacGoudsmit/P1V.
The Altera 5CEFA9F23C8 Cyclone V FPGA which has 113560 ALM's (claimed to be equivalent to about 301K LE), and an ARM Cortex A9 processor as well as two hard memory controllers, one of which is connected to 128KB DDR3 RAM (edit: I was mistaken about the ARM processor). The board also contains an Ethernet PHY and connector, and a MicroSD card reader. Parallax are working on a development board with the same FPGA to let enthusiasts explore the new Propeller 2 while it's not finalized yet.
Instructions on how to build the P1V project for the BeMicroCV-A9 using the free Quartus II Web Edition (version 15 or later) are in the readme.txt file in the P8X32A_BeMicroCV-A9 directory in the repository. There is also a picture showing how the Propeller pins are connected to the pin header. You will need a Prop Plug to program the P1V using one of the Propeller programming tools. The on-board EEPROM unfortunately isn't big enough to hold a Propeller program and it isn't connected by default, but you can download programs to RAM and execute them from there.
On my 3.1 GHz quad-core i5-2400 with 8GB of RAM, compilation takes about 7 minutes. The result uses 8552 ALM's (8% of 113560) and 655,360 block memory bits (5% of 12492800), one PLL (of eight). The current design doesn't use the DDR3 Hard Memory Controller or any other peripherals on the board.
===Jac
The Altera 5CEFA9F23C8 Cyclone V FPGA which has 113560 ALM's (claimed to be equivalent to about 301K LE), and an ARM Cortex A9 processor as well as two hard memory controllers, one of which is connected to 128KB DDR3 RAM (edit: I was mistaken about the ARM processor). The board also contains an Ethernet PHY and connector, and a MicroSD card reader. Parallax are working on a development board with the same FPGA to let enthusiasts explore the new Propeller 2 while it's not finalized yet.
Instructions on how to build the P1V project for the BeMicroCV-A9 using the free Quartus II Web Edition (version 15 or later) are in the readme.txt file in the P8X32A_BeMicroCV-A9 directory in the repository. There is also a picture showing how the Propeller pins are connected to the pin header. You will need a Prop Plug to program the P1V using one of the Propeller programming tools. The on-board EEPROM unfortunately isn't big enough to hold a Propeller program and it isn't connected by default, but you can download programs to RAM and execute them from there.
On my 3.1 GHz quad-core i5-2400 with 8GB of RAM, compilation takes about 7 minutes. The result uses 8552 ALM's (8% of 113560) and 655,360 block memory bits (5% of 12492800), one PLL (of eight). The current design doesn't use the DDR3 Hard Memory Controller or any other peripherals on the board.
===Jac
Comments
Did they change the CV-A9? I did not think it used the SoC version which has the ARM processor on board. Or did they include soft IP to load a compatible ARM core into the FPGA?
If they are using the SoC A9 version then that amazing price just went unbelievable...
Have not ordered mine yet but now I really want to get that done.
Keep up the good work!
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=836
It's still good value for money.
It appears I was mistaken, the FPGA that's on the BeMicroCV-A9 doesn't have an ARM on board. Altera type numbering is confusing, and I guess the A9 in the type doesn't stand for "Arm 9". I corrected the original post. Apologies for the misunderstanding.
Nevertheless, the A9 gives you a LOT of room to play around with (you could build a system with ten virtual Propellers and still have room to spare), for a very reasonable price. I wouldn't be surprised if Arrow takes a loss on every single board of that type that they sell. I really want to support Parallax and I'm still planning on buying the final 1-2-3 board once it's released, but for now, the BeMicroCV-A9 was what I could afford.
===Jac
How many errors did the compilation throw?
Critical warnings are:
- No exact pin locations for 7 pins of 56. This is caused by the fact that the J1 header has a couple of pins that aren't connected to the FPGA (5V / 3V3 / GND / NC) but I declared J1 as a single 40 pin port on the top level entity. This makes Quartus connect the unused port wires to other FPGA pins which is not a big deal until you also start using the J2 and J4 headers in the same way: it runs out of unused FPGA pins. I'll see if I can do something about that, but it's not super important right now.
- The TimeQuest Timing Analyzer fails because it can't find a constraints file. Seairth created files for the Cyclone IV targets but I think he said they won't work for Cyclone V. I may figure out how to generate or write a file to fix the timing but for now I'll leave it alone.
Other warnings:- Objects rom_low and rom_high are never assigned (and there are messages about the ROM dump files having an unexpected format which Quartus fixes correctly): I'm planning on rewriting the hub_mem module again so they use $readmem for compatibility (currently they use an Altera specific initializer construct) and so it's easier to reconfigure the ROMs for smaller devices like the DE0. I did this before in the old depot and I think it made these warnings disappear.
- Clock multiplexers found and protected: not sure why this is a warning
- Bidirectional ports have no drivers / Design contains input pins that drive no logic / Some pins have incomplete I/O assignments / Pins have permanently disabled output-enable: again a result of declaring J1 as a 40-bit wire, can be safely ignored
- RST and LOCKED ports on the PLL not properly connected. These can probably be safely ignored because we only use one hard PLL and all other clocks are derived from it so it doesn't cause any race conditions.
- Feature LogicLock only available with a subscription license: that's a matter of disabling it in the settings
- Found invalid Fitter Assignments: caused by the fact that I assigned all pins from the reference guide (including the DDR3 and Ethernet pins) but didn't use them in the design.
I didn't do a lot of testing, I just ran my little test program (in the Spin directory) that starts all the cogs one by one to let the LEDs light up.I'm thinking of designing a small circuit board with a couple of 40-pin headers to make it possible to use QuickStart boards with the BeMicroCV and BeMicroCV-A9. It will also have an EEPROM and maybe an FTDI chip and a transistor+RC circuit(*) to emulate a Prop Plug.
===Jac
(*) It's easy to eliminate the Transistor/RC circuit by connecting the RTS or DTR straight to the FPGA and emulating the pulse on the reset line in Verilog. I wonder how hard it would be to find some Verilog that eliminates the FTDI chip :-)
Sounds good - I'd suggest including a SPI flash memory of the same type the P2 will ultimately use when booting, and perhaps a couple of QuadSPI SRAMs ?
For easier, Quick USB at low cost, there is also this
www.digikey.com/product-detail/en/CP2104-MINIEK/336-2613-ND/
Good idea! Prepare for the P2.
Edit: But see my next post below...
===Jac
Parallax's 1-2-3 boards are in between with the CVA7. And I am hoping that most of the migration issues from the CV to CVA9 will be similar to migration from the CVA7 to CVA9.
I never did comprehend the ARM Cortex A9 mention and am VERY HAPPY to hear that it is NOT part of the scheme. Reading all these technical abbreviations certainly can lead one off in the wrong direction.
+++++++++
At this point, I will try to re-read this whole thread with an eye toward what successes you have had with attempting to compile a P2 image on the CVA9.
+++++++++
I am not too sure that adding a lot of expensive 'goodies' to a daughter board is a good idea. I'd settle for one that does basic interfacing elements that appear lacking on the BeMicroCV and the BeMicroCVA9.... appeal to the broadest base of potential buyers.
If you desire some fancy add-ons of costly chips, maybe provide the circuitry but sell the board without those chips installed. You sale price will be lower and those that really want the feature can procure and fit them. That adds value to the board while not adding production costs. Not sure if the QuadSPI SRAMs are in the expensive side of things or not.
If you desire some fancy add-ons of costly chips, maybe provide the circuitry but sell the board without those chips installed. You sale price will be lower and those that really want the feature can procure and fit them. That adds value to the board while not adding production costs. Not sure if the QuadSPI SRAMs are in the expensive side of things or not.
If a board is sold without chips fitted, then the incremental cost of adding QuadSPI memory is in the noise.The PCB area is likely there anyway, and 2 x SO8 footprints are not complex design.
On another front, I have had difficulty sorting out what A-2, A-7, and A-9 actually imply amongst the Cyclone chips. I think these are all Cyclone E devices. So attached is a PDF taken from a Cyclone V manual.
The A-9 devices seem to have twice the embedded memory resources of the A-7. The A-2 would be the BeMicroCV, the A-7 would be the Parallax 1-2-3, and the A-7 would be the BeMicro A-9.
Working through the Cyclone V manual, there are a lot of other differences (and similarities) mentioned between these three. So I am not sure what else may or may not be relevant.
Here is the link to the whole manual, search using Find for A2, A7, and A9.
www.altera.com/.../hb/cyclone-v/cv_5v2.pdf
But I am a bit uncertain that they are all the Series E Cyclones or if some are and some are not
Does this not help ?https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/pt/cyclone-v-product-table.pdf
jmg, thank you.
It certainly does!!!!!!!!!!!! Sums it all up.
i am sure I will still be turning to the manual to figure out what this numbers really mean.
In my thread about aiming for a clean compile I worked out the ROM files for various versions and they are posted there. This should help, together with other fixes, to minimise the errors/warnings.
I had a glance at the 1-2-3 board schematics, and it looks like it has no QuadSPI RAM on board. It makes sense: I think the idea is that the 1-2-3 board only emulates the parts that are (highly likely to be) inside the P2, not any peripherals that you would attach to it.
Actually, now that I think about it, I don't think Parallax will supply a P2 image for the BeMicroCV-A9 anyway. They invested significant resources into the 1-2-3 board and made it so specific to the P2 features that it's not worth investing even more effort to generate another image for a completely different board with a lot of missing features. Even if I (or someone else) would make a PCB to connect to the J1 and J4 headers, it's still only just enough for the 64 digital I/O pins. There's no way to make a single PCB that connects to J1 and J4 and also connects to J2 (the edge connector). And even if Chip wants to put in the trouble of creating an extra BeMicroCV-A9 revision in his Quartus project for the BeMicroCV-A9, it will take him significant extra time to compile it every time.
So I think I'll just make a board that will benefit those who have a BeMicroCV or BeMicroCV-A9 (and maybe the DE0-Nano and DE2-115) and want to connect the P1V to standard P1 peripherals.
===Jac
In my thread about aiming for a clean compile I worked out the ROM files for various versions and they are posted there. This should help, together with other fixes, to minimise the errors/warnings.
I'm definitely going to look at that. Unscrambling the ROM code and re-implementing other features that we already had in the old repo are definitely on the agenda but I'm very busy so I don't know when this is going to happen. If you guys could do your work in Github instead of posting ZIP files to the forum, it would really make things a lot easier...
===Jac
Actually, now that I think about it, I don't think Parallax will supply a P2 image for the BeMicroCV-A9 anyway. They invested significant resources into the 1-2-3 board and made it so specific to the P2 features that it's not worth investing even more effort to generate another image for a completely different board with a lot of missing features.
I take the opposite view.
Parallax are looking for test coverage,and a BeMicroCV-A9 gives them that.
They have moved the 1-2-3 board to the A9, and so will mainly build for that A9 chip.
The A7 will be a smaller subset build, that will be needed, but only for the few Rev1 boards.
Missing QuadSPI on the 1-2-3 is frankly surprising, as they are small. and are a highly likely connected device.
The whole idea of 1-2-3 is test coverage, and that includes likely peripherals, not just the core alone.
If I was doing an adapter board, I'd include a HyperBUS RAM device too (BGA only for now)
Parallax are looking for test coverage,and a BeMicroCV-A9 gives them that.
I hope you're right and I hope they'll support it! But I guess what I was trying to say is that the schematics for the 1-2-3 and the BeMicroCV-A9 are so different that a P2 image for the 1-2-3 board will not work. And given the amount of effort they put into the 1-2-3 board, I think we shouldn't expect support for the BeMicroCV-A9 although it would be nice if they will support it.
The bottom line is that I don't want to design some piece of hardware that would only be useful with a P2 image, unless I know that that hardware would be useful. I have some idea of the effort that it would take for Chip to support the BeMicroCV-A9 as well as the 1-2-3 board and I hope that he'll put in that effort (especially since, as you say, he already promised he'll support two versions of the 1-2-3 board and more testers mean more testing), but I'm not counting on it. If they don't support the BeMicroCV-A9, there's no way of changing a 1-2-3 image file to change pin assignments and do other magic, and they won't release the Verilog source either I don't think. So there's no point in trying to get ahead of Parallax to design some sort of hardware to make the BeMicroCV-A9 into some sort of limited 1-2-3 board clone.
===Jac
Have you checked how the 123 A7 pins line up with the BeMicro CV-A9? I'm sure we could find some overlap pins for supporting things like SPI flash memories.
Whether the BeMicroCV-A9 will be supported - I'm not sure whether even Parallax would know. Maybe later? I suspect it's not that big a deal to compile for it, but it's useful if everyone is testing with the same dev hardware rather than splitting off into camps, at least initially.
Pin 1 this top left corner|vNC P6P9 P7P5 P10P8 P11P4 P465V GNDP0 P1P41 P40P63 P62NC NCP2 P3P28 P29P24 P25P20 P213v3 GNDP16 P17P42 P43P50 P51P52 P53P58 P59
However I P0-P31 are 3v3 gpio, and P32-P63 are 2v5 gpio. You have 20 3v3 gpio pins available, including a contiguous P0-P11, then P16-17, P20-21, P24-25, P28-29plus 13 2v5 gpio (scattered)
Hopefully that might be enough common to make something universal, though.
Have you checked how the 123 A7 pins line up with the BeMicro CV-A9? I'm sure we could find some overlap pins for supporting things like SPI flash memories.
Yes there is some overlap, but it will be necessary for Chip to do a separate build for the CVA9 either way. He would have to create a different .qsf file for the CVA9 (feel free to start off with the one in my Github, Chip) and he would probably have to deal with a reduced number of available pins. If I counted correctly, there are only 33 assignable pins on J1 and only 12 on J4. There are 56 pins on the edge connector J2 but if you use that, it means having to find a connector and possibly a cable and a header on the expansion board.
Whether the BeMicroCV-A9 will be supported - I'm not sure whether even Parallax would know. Maybe later? I suspect it's not that big a deal to compile for it, but it's useful if everyone is testing with the same dev hardware rather than splitting off into camps, at least initially.
I expect that a compile for the P2 will take significantly longer than the compile for the P1, so depending on how often Chip will want to do the compile, the extra time waste can be a real annoyance.
On the one hand it's better if there are no distractions caused by people trying to test with different hardware but on the other hand it could be useful to test with maximum hardware variation. They'll have to weigh one against the other. We'll see what they decide.
===Jac
I thought someone has posted a part number for that connector ?
...
However I think P0-P31, and P32-P63 have different voltages. One's 3v3 and one's 2v5, but going from memory
Right, on the CVA9 all the I/O bank power supply voltages are tied to one jumper that selects 2.5V or 3.3V. Not a big deal I think.
The problem is that if you would somehow be able to download a 1-2-3 image onto a CVA9, the P2 would be talking to the Ethernet hardware, DDR3 chip and MicroSD controller instead of the D/A converters. I don't know how that would turn out.
But because the 1-2-3 uses the Propeller and a custom tool to download the image, I reckon it's going to be impossible to use a P2 image with the CVA9 anyway. Again, we'll see.
===Jac
But because the 1-2-3 uses the Propeller and a custom tool to download the image, I reckon it's going to be impossible to use a P2 image with the CVA9 anyway. Again, we'll see.
Good point - the P2 FPGA image itself should be not such a problem, as any board has to be able to Program the FPGA
Trickier may be frequent update to BOOT flash, and RST -> native P2 load from that.
ie 'normal' P2 use cycling.
One fish-hook is around FLASH Addressing, as 128Mb/256Mb is where it jumps from 3 byte to 4 byte addressing.
I found this :
http://www.macronix.com/Lists/ApplicationNote/Attachments/855/AN0209 - High density_Serial_Flash_Addressing.pdf
Simplest is probably to just add a dedicated P2-Boot SPI Flash device, and Flash loader (CP2130?).
Not sure what Parallax did on the 1-2-3 Board.
Addit: I see the CV A9 BOM follows Arrows's standard recipe of FT245+5M80ZE64C5N CPLD, so no COM channels for users here.
That leaves a serial boot choice on P2, but an external COM adapter is needed for that too.A direct Flash loader (CP2130) would download faster than a standard P1 COM loader, but is a little 'non std'.
Lattice have a nicer approach, they commonly use a FT2232H (dual) and give users a SPI link for JTAG and a Serial Port for user channel debug.
I ran a similar exercise on the 80 pin expansion. It contains largely the 48 pin expansion slot pins used with the Prop123, with the notable exception of 4 pins, expm[0] through [3]. So very close. There are a couple of gpio on there, P13, P60, P61, perhaps these can help to bridge.
If the P2 boots in the normal manner, with pins as inputs, we should be ok. The vccio voltages will be compatible due to the hardware design (so long as we observe 3v3 / 2v5 rules for whatever connects to gpio as mentioned earlier). So the peripherals on the BeMicroCV A9 might not line up nicely, but I don't think that's a show-stopper
...
However I think P0-P31, and P32-P63 have different voltages. One's 3v3 and one's 2v5, but going from memory
Right, on the CVA9 all the I/O bank power supply voltages are tied to one jumper that selects 2.5V or 3.3V. Not a big deal I think.
The problem is that if you would somehow be able to download a 1-2-3 image onto a CVA9, the P2 would be talking to the Ethernet hardware, DDR3 chip and MicroSD controller instead of the D/A converters. I don't know how that would turn out.
But because the 1-2-3 uses the Propeller and a custom tool to download the image, I reckon it's going to be impossible to use a P2 image with the CVA9 anyway. Again, we'll see.
===Jac
Oh my! I was seduced into thinking that because the CVA7 and the CVA9 have exactly the same 440 pins and Parallax eventually intends to use the CVA9 on the Propeller 1-2-3 that all would be fine.
Simply put, it seems you believe the features on the BeMicro CVA9 will block the ability to clone what the Propeller 1-2-3 will do unless a lot of Frankenstein recoding could succeed.
In a way, I am happy to hear this as it establishes that the Propeller 1-2-3 A7 and A9 boards do have an added value that justifies the higher cost.
I went with the BeMicro CVA9 and it may be a longer wait and a tougher slog to get Propeller 2 emulation. But I still am happy with it. And curious about the potential to add its hardware features to the Propeller IV - like the network interface.
IOW, there are ways to enjoy the BeMicro CVA9 other than just for the Propeller 2 image.
The pin differences between the CVA7 and CVA9 are apparently minor (as pointed out by Chip/Ken), but the differences between how the pins are used on the 1-2-3 and the BeMicroCV-A9 are non-trivial. Since Chip will be the only person with the source code, support for the BeMicroCV-A9 for the P2 will depend on him.
Meanwhile, yes, the BeMicroCV-A9 can be useful in so many other ways!
===Jac