DE0-Nano-SoC Kit/Atlas-SoC Kit
Bill Henning
Posts: 6,445
There is a new DE0-Nano in town...
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=163&No=941&PartNo=2#section
Looks very interesting, decent price as well.
40k LE's instead of 22k (old Nano), dual core A9 ARM with 1GB DDR3, and a lot more.
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=163&No=941&PartNo=2#section
Looks very interesting, decent price as well.
40k LE's instead of 22k (old Nano), dual core A9 ARM with 1GB DDR3, and a lot more.
Comments
I did a P1V compile for this device a few weeks ago and managed to squeeze 2 x P1V's into it.
The downside was it took Quartus 15.0 over 90 minutes to compile and used ~95% of the logic.
1GB RAM + Dual Core ARM A9 + 2 x P1V's = Serious Fun
However, the Cyclone V family adds serious compile time to Quartus 15.0 and there also seems to be a serious hit with logic usage.
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=836
A lot more expensive, but it has a larger Cyclone V with 85K LEs and some other stuff: