Learning HDL
evanh
Posts: 15,918
With the release of Quartus v15 it now works with my Linux distro, Kubuntu 14.04, so I've started dabbling with the P1V source that Parallax have so kindly provided us.
First thing that stands out is a need for me to understand the details of Verilog code. How the various operators translate to logic gates for example. To that end I look up the provided help documents ... first one I come across that looks promising is the "Quartus II Introduction for Verilog Users" PDF. I get to page 12 where they present an n-bit adder in schematic form, quite the beauty to behold. It's just the sort of example I'm looking for ... and on next two pages they present the source to generate it but, sadly, with no further explanation of the language.
I page through a bit further until I come to page 25 (Section 5) - Using the RTL Viewer - and there's a picture of a windowed schematic, I'm intrigued, can this RTL viewer show me the whole Prop in schematic form? I'd already compiled the P1V source earlier ... I stop reading and start clicking ... and found with a right click on any hierarchy entity and choosing Locate Node -> Locate in RTL Viewer did the trick. Viola! Choosing Top entity gives the whole Prop in a tiny few boxes.
Now to start learning the language for real ... I open up a bunch of views and note there is distinct lack of net naming and no way to enquire either. Not a show stopper luckily, since I can narrow things down by entity names, ... I also notice some odd, for typical schematic, operators, ie: use of shifters for address decoding, so I compare it with the source ... and sure enough the RTL Viewer is showing me the same logic as what's in the Verilog source. All good so far.
I've attached an example of one detail I've learned, the & operator being used as a single logic bit. I've selected the relevant line in the source and mem_w is highlighted red in the schematic.
BTW: Interestingly, RTL Viewer fails to show inverted outputs on logic gates. It seems to be a bit of a work in progress.
First thing that stands out is a need for me to understand the details of Verilog code. How the various operators translate to logic gates for example. To that end I look up the provided help documents ... first one I come across that looks promising is the "Quartus II Introduction for Verilog Users" PDF. I get to page 12 where they present an n-bit adder in schematic form, quite the beauty to behold. It's just the sort of example I'm looking for ... and on next two pages they present the source to generate it but, sadly, with no further explanation of the language.
I page through a bit further until I come to page 25 (Section 5) - Using the RTL Viewer - and there's a picture of a windowed schematic, I'm intrigued, can this RTL viewer show me the whole Prop in schematic form? I'd already compiled the P1V source earlier ... I stop reading and start clicking ... and found with a right click on any hierarchy entity and choosing Locate Node -> Locate in RTL Viewer did the trick. Viola! Choosing Top entity gives the whole Prop in a tiny few boxes.
Now to start learning the language for real ... I open up a bunch of views and note there is distinct lack of net naming and no way to enquire either. Not a show stopper luckily, since I can narrow things down by entity names, ... I also notice some odd, for typical schematic, operators, ie: use of shifters for address decoding, so I compare it with the source ... and sure enough the RTL Viewer is showing me the same logic as what's in the Verilog source. All good so far.
I've attached an example of one detail I've learned, the & operator being used as a single logic bit. I've selected the relevant line in the source and mem_w is highlighted red in the schematic.
BTW: Interestingly, RTL Viewer fails to show inverted outputs on logic gates. It seems to be a bit of a work in progress.
1000 x 1600 - 209K
Comments
All inverted outputs in RTL are omitted ---- Them are instead placed on INPUT of next stage's Logic as small round circle
Doh! Looking at the schematics, that's so obvious now. Thank you Sapieha.
BTW Hi Sapieha.
That seems to be an excellent place to start.