code execution in sync with external 5MHz clock

iammegatron

I am trying to convince my boss to migrate a fpga design for signal demodulation to propeller mcu.

Basically, the propeller assembly code needs to be executed in synchronous with an external clock signal, which is running at 5 MHz.

I know there can't be many assembly instructions to be executed within 200ns. So I divided down 5 MHz clock, in order to have time to run more assembly instructions on propeller. The key requirement is to be in sync. (easy for fpga to do)

Here is my code snippet:

dat
          org
entry   mov ctra, ctra_    'edge detection on APIN (input 5MHz clock)
          mov frqa, #1

          mov outa, #0                  'zero output pins
          or dira, pin_13_mask      'set pin13 as output

       
read    test mask, phsa wc
          ' do signal demodulation here
          ' some code
  if_c   or outa, pin_13_mask  
  if_c   jmp #read
          andn outa, pin_13_mask
          jmp #read 
        

ctra_ long %01010<<26 + 14     ' APIN = 14
mask  long %1<<2                   ' bit to divide down clk signal from APIN
pin_13_mask long %1<<13
      

PIN_13 output the divided down (1/8) of 5 MHz clock signal.

Just wondering if there is a better solution?

Cluso99

Not sure just what you are trying to achieve here.

However, the propeller can use an external 5MHz clock instead of a xtal. The prop internally generates 16* this frequency, so the prop will run at 80MHz.
Each prop instruction normally is 4 clocks (a jump/call/etc not taken will take 8 clocks excepting if its not taken due to a condition such as if_c which will always be 4 clocks). rdxxxx/wrxxxx to hub takes up to 16 clocks.

You can also use waitpeq/waitpne for a pin to transition low/high which will sync within 1 clock (12.5ns).

Hope this helps. If not, tell us more about what you are trying to do.

BTW you can also overclock the prop with careful pcb/decoupling designs. I typically clock at 104MHz on my boards.

jmg

iammegatron wrote: »

I am trying to convince my boss to migrate a fpga design for signal demodulation to propeller mcu.

Basically, the propeller assembly code needs to be executed in synchronous with an external clock signal, which is running at 5 MHz.

Is that a continual clock, of low jitter ?
If yes, then you can use as external clock, and PLL to that, which will have a fixed phase relationship on Prop opcodes
You can sync to that edge ( or divided edges) with a WAITxx instruction, which is 12.5ns granular at 80MHz.
You may need to experiment with inversion on the PLL/Test pin, as the PLL will sync to one edge of the CLK, and you want to avoid sampling at exactly the same time.
Provided you avoid the same-edge test, the code will sync in time << 12.5ns, because the PLL is also locked

Heater.

Can any one advise when the problem you are trying to solve is not stated?

You mention "signal demodulation". What kind of signal is that? What modulation? What frequency/data rate?