New Unscrambled P1V ROM with Faster Spin Interpreter
Cluso99
Posts: 18,069
18th April 2015: See Post #16 for the latest files.
See Post #3 for latest files, including ROM files for both the P1 Spin Interpreter, and (my) Cluso's Faster Spin Interpreter.
Here are modified Verilog files (from the latest git files) to be updated to use unscrambled roms (also posted)...
rom_low_v028.hex (hub $8000-$BFFF)
rom_high_v028.hex (hub $C000-$FFFF)
hub.v (unscrambling removed as no longer required with the above hex files)
hub_mem.v (use new hex files)
I have removed these files - see post #3 for the latest files
See Post #3 for latest files, including ROM files for both the P1 Spin Interpreter, and (my) Cluso's Faster Spin Interpreter.
Here are modified Verilog files (from the latest git files) to be updated to use unscrambled roms (also posted)...
rom_low_v028.hex (hub $8000-$BFFF)
rom_high_v028.hex (hub $C000-$FFFF)
hub.v (unscrambling removed as no longer required with the above hex files)
hub_mem.v (use new hex files)
I have removed these files - see post #3 for the latest files
Comments
Line 99 should be uncommented and Line 100 should be commented out thus...
hub.v & hub_mem.v are Verilog files for using unscrambled roms.
rom_low_v030.hex, rom_high_v030.hex & rom_cluso_v030.hex are unscrambled roms for lower rom $8000..$BFFF, upper rom $C000..$FFFF, and my new upper rom $C000..$FFFF using my "Faster Spin Interpreter". WARNING:My ClusoInterpreter overwrites a section of the SIN table from $EC00..$EFFF, so that the SIN table is effectively unusable!
roms_v030_20150412.zip
hub_v030_20150412_unscrambled.zip
There are no code mods to the P1V other than I removed the de-scrambler, and of course a new default ROM (which steals 1KB from the SIN table).
However, some prelim tests I have done is not showing the speed up I had calculated
But there is spare space to make further improvements to the interpreter.
As you can see, I haven't tested subroutines/repeats etc, just the basic mathops.
I was pleased to see the P1 and the P1V with P1 ROMs performed identically, as they should.
What is the size difference ? If you can gain room for more features, then the gains could be made there.
eg can you add debug options and still meet speed ?
A special case would be a Faster Spin Interpreter, with Debug tests added, and set to run at the same speed as original spin. Now, you have good Debug coverage, and the code should be identically timed ?
http://forums.parallax.com/showthread.php/142803-Some-multi-language-benchmarks?highlight=language+benchmarks
There is now some small space remaining in the cog once loaded, so some other improvements can be made.
My Debug can be added, but requires the support of hub space. It runs considerably slower because it is running the interpreter in LMM mode.
A lot depends on the debugger and the facilities required. It's not possible to return to the same speed as the original interpreter with my version. There is too much intertwining of code in Chip's interpreter to make it fit.
An alternative would be to always report PC into HUB, and have another COG doing a profile like trace.
jazzed also did a debugger, but don't recall its features or what it was called.
BMA
That looks impressive, but seems an old and surprisingly short thread for such a gem ?
Is it still active, or does it rely on BSTC ?
There is an other gem by Jazzed
It has my Faster Spin Interpreter (ClusoInterpreter) which now fits the vector table in without requiring the loss of the SIN table.
I have rearranged the runner into 3 parts to free a space for the vector table. The booter has the mods done by ozpropdev to report
the correct version if hub > 64KB.
The propeller version is identified as "3".
The rom is unscrambled. You will require the modified hub.v and hub_mem.v Verilog files and the cluso_romhi_031.hex file.
cluso_romhi_031.hex is composed of the additional files included in the zip file.
This is the hub high rom memory map...
cluso_romhi_031.zip
hub_mem_031.zip