Faster clock in P1V ? Faster hub 1:8 ? Results anyone???
Cluso99
Posts: 18,069
I see ozprop has faster clocking available in his Verilog generator.
Has anyone done any tests with faster clocking that doesn't produce timing errors and of course seems to work?
If yes, what speed and what boards?
Has anyone tried to speedup hub access to 1:8 instead of 1:16?
If yes, what code did you change?
Am I correct to believe we can get 60KB of hub with the BeMicro CV?
Has anyone done any tests with faster clocking that doesn't produce timing errors and of course seems to work?
If yes, what speed and what boards?
Has anyone tried to speedup hub access to 1:8 instead of 1:16?
If yes, what code did you change?
Am I correct to believe we can get 60KB of hub with the BeMicro CV?
Comments
I had a Max10 running @ 133MHz with no obvious problems.
Here are Hub ram sizes determined from my tests.
128k Be-Micro CV
288k DE0-CV
416k DE2-115
640K Parallax 1-2-3
These results are based on real builds done on a new revised Verilog code generator I hope to post very soon.
Cheers
Brian
Compiling DE0_nano gives timing errors (2) with 133MHz but 100MHz seems fine.
Looking forward to seeing your new Verilog generator.
DE1-SoC. 180 MHz running; don't know if full stable. 200 MHz not running. No more tests done; I used DE2-115 then.
Did you get any clean compiles with any of these higher speeds?
Do you have some 'stability-stress-test' code that others can use, when verifying what clocking margin their build has ?
Seems it could be a good idea to have both timing reports, and silicon verify of some margin above that reported value, just to make sure... - plus some will always want to overclock