Shop OBEX P1 Docs P2 Docs Learn Events
Faster clock in P1V ? Faster hub 1:8 ? Results anyone??? — Parallax Forums

Faster clock in P1V ? Faster hub 1:8 ? Results anyone???

Cluso99Cluso99 Posts: 18,069
edited 2015-04-08 13:05 in Propeller 1
I see ozprop has faster clocking available in his Verilog generator.

Has anyone done any tests with faster clocking that doesn't produce timing errors and of course seems to work?
If yes, what speed and what boards?

Has anyone tried to speedup hub access to 1:8 instead of 1:16?
If yes, what code did you change?

Am I correct to believe we can get 60KB of hub with the BeMicro CV?

Comments

  • ozpropdevozpropdev Posts: 2,792
    edited 2015-04-05 02:38
    Ray
    I had a Max10 running @ 133MHz with no obvious problems.
    Here are Hub ram sizes determined from my tests.
    128k Be-Micro CV
    288k DE0-CV
    416k DE2-115
    640K Parallax 1-2-3
    These results are based on real builds done on a new revised Verilog code generator I hope to post very soon.
    Cheers
    Brian
  • Cluso99Cluso99 Posts: 18,069
    edited 2015-04-05 03:08
    Thanks Brian.
    Compiling DE0_nano gives timing errors (2) with 133MHz but 100MHz seems fine.

    Looking forward to seeing your new Verilog generator.
  • pik33pik33 Posts: 2,366
    edited 2015-04-07 10:31
    DE2-115: Propeller works up to 145 MHz but this is unstable. Full stability clock is something near 120 MHz. I use 114 MHz in the retromachine; this is stable.
    DE1-SoC. 180 MHz running; don't know if full stable. 200 MHz not running. No more tests done; I used DE2-115 then.
  • Cluso99Cluso99 Posts: 18,069
    edited 2015-04-07 16:22
    Thanks pik33.
    Did you get any clean compiles with any of these higher speeds?
  • pik33pik33 Posts: 2,366
    edited 2015-04-08 12:38
    No, and I don't care. I learned some tricks to make it work without these awful timing files :) No clean compiles at all, but the P1V in retromachine is rock stable @ 114 MHz; the stability limits are in vga/sram conroller working @ 152 MHz.
  • jmgjmg Posts: 15,173
    edited 2015-04-08 13:05
    pik33 wrote: »
    No, and I don't care. I learned some tricks to make it work without these awful timing files :) No clean compiles at all, but the P1V in retromachine is rock stable @ 114 MHz; the stability limits are in vga/sram conroller working @ 152 MHz.

    Do you have some 'stability-stress-test' code that others can use, when verifying what clocking margin their build has ?

    Seems it could be a good idea to have both timing reports, and silicon verify of some margin above that reported value, just to make sure... - plus some will always want to overclock
Sign In or Register to comment.