When using a fast FPGA, it may be possible to clock the hub at 2x the cog speed and effectively permit a 2:8 access (ie each cog sees 1:4).
A question..
Are the FPGAs (Cyclone IV, Cyclone V, Spartan 3, Spartan 6) true dual port RAM or can a read/read or read/write (not write/write) take place simultaneously (I forget)?
You can simultaneously perform one read and one write operations to different locations where the write operation
happens on port A and the read operation happens on port B.
True dual-port RAM
You can perform any combination of two port operations: two reads, two writes, or one read and one write at two different clock frequencies.
and the sizes are the same, but the possible Width/Depth ratios change - simple mode seems to allow wider access in a single block. ie 20w is True limit, needing 2 blocks for 512 x 40.
Note Cyclone V also has wider memory, 10 bit s vs 9 bits, but that is unusual, so using 40w would be unique.
36w is more universal, with 4 'free-bits'.
When using a fast FPGA, it may be possible to clock the hub at 2x the cog speed and effectively permit a 2:8 access (ie each cog sees 1:4).
A question..
Are the FPGAs (Cyclone IV, Cyclone V, Spartan 3, Spartan 6) true dual port RAM or can a read/read or read/write (not write/write) take place simultaneously (I forget)?
All FPGAs from Xilinx does support true dual port RAM in different configurations of width and size, i.e. if using 32 bit width the size is 512 and you can have additional 4 bits extra width which is reserved for parity but there is no parity logic implemented.
For Xilinx it will depend if working in synchronous or asynchronous mode (synchronous is when the active edges of both port clocks occur simultaneously). If in Asynchronous mode, "the READ_FIRST mode should be avoided" (the WRITE_FIRST mode is the recommended mode). In synchronous mode: "the other port can reliably read data from the same location if the write port is in READ_FIRST mode only".
From documentation is seems that Xilinx have made a much better job on memory blocks than Altera (both in size widths and control optioins).
Even Lattice XP2 has more ram WIDTH than any Altera (Cyclone IV/V or MAX-10). But less total ammount (number of blocks) overall.
Xilinx-7 : 1Kx32
Spartan-6 : 512x32 or 512x36
Cyclone-V : 256x32 or 256x40
Lattice XP2 : 1Kx18
MAX-10 : 512x18
Single port mode:
Xilinx-7 : 512x72 (Amazing, I am waiting for XC7A15T)
Lattice allows 512x36 (P1V Cog RAM without chaining blocks).
Altera needs to chain blocks to fit P1V COG ram.
For almost the same price, I'd rather prefer a Lattice XP2 with external SRAM than a MAX-10. And I wish ICE40 have had 18K blocks at the same price!
When XC7A15T comes it will make a 64 (or 72) bit propeller possible. The only elegant solution to our opcode size / cog ram misery. Don't care about code efficiency or DMIPS/MHZ. We don't need that. Its all about IO bandwidth. Go ahead, lets do a 96 bits or 128 COG !
@Heater,
I sent you a PM explaining the indefinte pronoun 'one'.
++++++++++++
Let's drop that one and get back to the Propeller as a topic.
@Everyone
I am enjoying following this thread as up until now, I have been trying to ignore buy a FPGA. But while waiting for the P2, the chance to investigate a variety of architectures gets more and more interesting.
Thanks. There maybe other late comers to the FPGA that are enjoying this.
OK. ignoring the "one" I think it's a good idea that any curious geek gets attracted to the world of FPGAs. How cool can it be to design your own logic circuits and not have to make a PCB and solder it all together? Just describe what you want in Verilog or VHDL, download it to your FPGA and there it is.
How cool can it be to design your own logic circuits and not have to make a PCB and solder it all together? Just describe what you want in Verilog or VHDL, download it to your FPGA and there it is.
It's the advanced way today of Chip's idea when the P1 was born. Do it with software!
Comments
A question..
Are the FPGAs (Cyclone IV, Cyclone V, Spartan 3, Spartan 6) true dual port RAM or can a read/read or read/write (not write/write) take place simultaneously (I forget)?
Simple dual-port RAM
You can simultaneously perform one read and one write operations to different locations where the write operation
happens on port A and the read operation happens on port B.
True dual-port RAM
You can perform any combination of two port operations: two reads, two writes, or one read and one write at two different clock frequencies.
and the sizes are the same, but the possible Width/Depth ratios change - simple mode seems to allow wider access in a single block. ie 20w is True limit, needing 2 blocks for 512 x 40.
Note Cyclone V also has wider memory, 10 bit s vs 9 bits, but that is unusual, so using 40w would be unique.
36w is more universal, with 4 'free-bits'.
For Xilinx it will depend if working in synchronous or asynchronous mode (synchronous is when the active edges of both port clocks occur simultaneously). If in Asynchronous mode, "the READ_FIRST mode should be avoided" (the WRITE_FIRST mode is the recommended mode). In synchronous mode: "the other port can reliably read data from the same location if the write port is in READ_FIRST mode only".
From documentation is seems that Xilinx have made a much better job on memory blocks than Altera (both in size widths and control optioins).
Even Lattice XP2 has more ram WIDTH than any Altera (Cyclone IV/V or MAX-10). But less total ammount (number of blocks) overall.
18 Kblocks: Xilinx Spartan-6, Lattice XP2
10 Kblocks: Cyclone's
9 Kblocks: Max-10
4 Kblocks: ICE40
True Dual Port (max. width):
Spartan-6 : 512x32 or 512x36
Cyclone-V : 256x32 or 256x40
Lattice XP2 : 1Kx18
MAX-10 : 512x18
Single port mode:
Lattice allows 512x36 (P1V Cog RAM without chaining blocks).
Altera needs to chain blocks to fit P1V COG ram.
For almost the same price, I'd rather prefer a Lattice XP2 with external SRAM than a MAX-10. And I wish ICE40 have had 18K blocks at the same price!
When XC7A15T comes it will make a 64 (or 72) bit propeller possible. The only elegant solution to our opcode size / cog ram misery. Don't care about code efficiency or DMIPS/MHZ. We don't need that. Its all about IO bandwidth. Go ahead, lets do a 96 bits or 128 COG !
@Heater,
I sent you a PM explaining the indefinte pronoun 'one'.
++++++++++++
Let's drop that one and get back to the Propeller as a topic.
@Everyone
I am enjoying following this thread as up until now, I have been trying to ignore buy a FPGA. But while waiting for the P2, the chance to investigate a variety of architectures gets more and more interesting.
Thanks. There maybe other late comers to the FPGA that are enjoying this.
Edit: Response shortened by request of Loopy.
OK. ignoring the "one" I think it's a good idea that any curious geek gets attracted to the world of FPGAs. How cool can it be to design your own logic circuits and not have to make a PCB and solder it all together? Just describe what you want in Verilog or VHDL, download it to your FPGA and there it is.
Edit: Junk removed.