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How about an Open Source P2-HOT?? — Parallax Forums

How about an Open Source P2-HOT??

mindrobotsmindrobots Posts: 6,506
edited 2015-03-22 08:18 in Propeller 2
Dear Parallax,

Since many of us had so much fun playing with the P2-HOT FPGA imagines (and some of us purchased expensive DE2-115 FPGA boards just to run it - no, I'm not bitter about that anymore...much).

Wouldn't it be cool/fun/exciting to release the Verilog for that wicked hot machine as Open Source?? The design of the new P2 is so radically different, it doesn't seem like you would be jeopardizing any potential P2 IP. It would be a great learning experience and give us some truly amazing features to work with and learn from. Making those of us that are trying to play along in the FPGA world all the more prepared for the P3 project.

Just a thought to keep us busy through the Spring!

What say ye???
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Comments

  • Ken GraceyKen Gracey Posts: 7,395
    edited 2015-03-09 20:40
    Rick, don't you think we should have working P2s in hand before we make such a move? :)
  • mindrobotsmindrobots Posts: 6,506
    edited 2015-03-09 20:56
    I'm referring to the Feb/Mar 2014, 8 COG, multi-thread, HUB Executing, water cooled, fire breather. I was assuming it's design was different enough from the P2 Chip is currently developing that there wasn't really any secret sauce left in the old P2 Verilog. I'd be happy to be wrong about that!

    I thought a never to exist in silicon P2-HOT in the hand was better than nothing in the bush for a while. (Wow, that just didn't word-smythe well at all! :D )
  • jmgjmg Posts: 15,175
    edited 2015-03-09 20:57
    mindrobots wrote: »
    Wouldn't it be cool/fun/exciting to release the Verilog for that wicked hot machine as Open Source??
    That was never quite finished, and it would represent a diversion of effort.
    There is P1V there now, if you want to play on FPGA boards, and hopefully even small boards will be able to test New P2 peripherals to get maximum coal-face experience and get software interaction / user control thrashed out so the stuff is solid before being 'cast in Silicon' .
  • jmgjmg Posts: 15,175
    edited 2015-03-09 20:58
    Ken Gracey wrote: »
    Rick, don't you think we should have working P2s in hand before we make such a move? :)

    No hints on a Verilog image release time frame for Cooler-P2-V0.1 ?
  • mindrobotsmindrobots Posts: 6,506
    edited 2015-03-09 21:07
    jmg wrote: »
    That was never quite finished, and it would represent a diversion of effort.
    I was more concerned about releasing any IP that might infringe on future Parallax designs. I don't get a diversion of effort at all. Release it "as is" with no guarantees, warranty or support. Put the code out on Github and let people play and learn....whose effort is diverted? Whoever decides to play with the P2-HOT? Chip and Parallax would stay focused on the real chip.
    There is P1V there now, if you want to play on FPGA boards, and hopefully even small boards will be able to test New P2 peripherals to get maximum coal-face experience and get software interaction / user control thrashed out so the stuff is solid before being 'cast in Silicon' .

    I missed the announcement about the New P2 peripherals.....what are those going to be? Where are all these small boards coming from, ready for testing? Parallax? Isn't that a diversion of effort? :D
  • jmgjmg Posts: 15,175
    edited 2015-03-09 21:15
    mindrobots wrote: »
    Isn't that a diversion of effort? :D
    If the tested elements end up in silicon, clearly no.
  • Ken GraceyKen Gracey Posts: 7,395
    edited 2015-03-09 21:41
    At this point, I'm not about to make a single request of Chip that takes even a minute away from the critical path of P2, even if it's a matter of "save-as".

    We don't want him spending his time here on the forums, either.

    Ken Gracey
  • ErNaErNa Posts: 1,752
    edited 2015-03-10 01:25
    A Chip in a cage! Deplorable Chip ;-( Thumbs up, times will change to the sunny side!
  • Dave HeinDave Hein Posts: 6,347
    edited 2015-03-10 06:07
    jmg wrote: »
    No hints on a Verilog image release time frame for Cooler-P2-V0.1 ?
    There have been a few hints. In Chip's interview from last month he hinted at having the Verilog done in 4 months, so that is now 3 months from now. Also, the P2 get-together in Rocklin is targeted for this Fall, and an announcement will be made 6 months prior when the FPGA image is ready. Well we're almost at 6 months before Fall starts, but assuming the get-together is at the end of Fall we're talking about the announcement being 3 months from now.

    So I'm hoping and expecting a P2 image within the next 3 months based on what Chip and Ken have said recently.
  • evanhevanh Posts: 16,041
    edited 2015-03-10 14:33
    One part missing in that time-line: FPGA proving time and bug fixes.

    EDIT: Speaking of which, what's the status of Parallax's own FPGA board? I haven't purchased any such boards as yet.
  • Dave HeinDave Hein Posts: 6,347
    edited 2015-03-10 14:55
    I assumed that was the 6-month period after the first FPGA image. I'm guessing that this time the initial FPGA image will be fairly complete since many of the components of the earlier versions can be re-used.
  • evanhevanh Posts: 16,041
    edited 2015-03-10 19:04
    Makes sense but I'm thinking when Ken said "Propeller 2 code is running in full on the Parallax FPGA 1-2-3 Development Board" he meant ready to delivery the design to On Semi. And from there being a six month process to sellable production.

    Ken's "schedule it" - http://forums.parallax.com/showthread.php/159884-Appreciation-and-Thanks?p=1313096#post1313096
  • Dave HeinDave Hein Posts: 6,347
    edited 2015-03-10 19:18
    There were 2 conditions for the "schedule it" milestone.
    - Propeller 2 code is running in full on the Parallax FPGA 1-2-3 Development Board
    - Manual layout of Propeller 2 is done by Treehouse Designs
    I'm assuming the first condition is to have a fully implemented FPGA image, but not fully tested by the community. The second condition must be the layout of the peripheral part of the chip. It seems that this can be done manually because it only needs to be done for one pin, and then replicated 64 times. I would assume the inner part of the chip will be laid out using automatic tools. So I don't think the "schedule it" milestone implies that the design is ready for On Semi.
  • evanhevanh Posts: 16,041
    edited 2015-03-11 01:29
    The FPGA work is only based on verilog and has no part of fitting. So, whoever does the fitting, it's still long after we're done with the FPGA stuff.

    I'm pretty confident all the FPGA work is prior the six month countdown.
  • Dave HeinDave Hein Posts: 6,347
    edited 2015-03-11 07:53
    evanh wrote: »
    I'm pretty confident all the FPGA work is prior the six month countdown.
    I don't believe that is the case. If what you are saying is true all of the FPGA testing would need to be done six months before the event in Rocklin. FPGA testing will probably take 6 months, so if Chip released an image today we probably wouldn't achieve the "schedule it" milestone until September, which means the event in Rocklin would be another 6 months from September, which is a year from now.

    EDIT: Maybe I misunderstand what you mean by "all the FPGA work". If you mean a complete FPGA image that implements all of the functionality, then I agree. However there will be additional FPGA work to fix problems that are found during testing. The additional FPGA work needs to be limited to bug fixes. If there is additional FPGA work to add new features the P2 will never be completed, and I don't think we'll ever see silicon. Parallax needs to put a stake in the ground and freeze all the features of the P2 if they ever want to actually produce the thing.
  • mindrobotsmindrobots Posts: 6,506
    edited 2015-03-11 08:15
    I'd say any date speculation is just an exercise in futility. Things will happen when they happen (or shortly after).

    I was looking for a better description of the intent and purpose of the "get together" in Rocklin.

    I did find this. In which Ken tells us:
    Prior discussion with Chip was that we'd announce the seminar date when we had our own, functional Propeller 1-2-3 FPGA board. I'll check with him to see what his latest thoughts are on this detail.

    So "schedule it" has three constraints:
    - Propeller 2 code is running in full on the Parallax FPGA 1-2-3 Development Board
    - Manual layout of Propeller 2 is done by Treehouse Designs
    - Availability of the Propeller 1-2-3 FPGA board.

    From what I recall, I see the event as a reception after the marriage of the FPGA image to the new board. The FPGA image and the new 1-2-3 board being the happy couple (boards for sale in the lobby).

    I'm unsure if there will be an FPGA release made for testing on DE2 or DE0 or anything else prior to ALL of those 3 milestones being complete.

    When it happens, it happens and whoever is around at the time can party like it's 1999! :D
  • Heater.Heater. Posts: 21,230
    edited 2015-03-11 11:17
    mindrobots,
    Wouldn't it be cool/fun/exciting to release the Verilog for that wicked hot machine as Open Source??
    Maybe. But in the long run it would be a waste of your time. It's a design that is deemed to have failed. Any programs or tools you might develop for it are a dead end. Any tweaks you make to it are dead end.

    All in all I feel you would be better off fetching a CPU design from opencores.org or perhaps the RISC V design.

    And hey, there is the P1 HDL to play with.

    That's before we get to the point of how much time it would waste for Parallax.
  • RamonRamon Posts: 484
    edited 2015-03-12 05:41
    To be honest, I think we must discourage parallax to publish any FPGA image of the new P2.

    What would happen if parallax publish the details and someone fills the design into the patent office on the same day? They don't even need to fill the patent for the whole IC, just one small thing (like smartpins / smartio or anything else).

    Or what would happen if they publish the opcode list and someone gets a trademark, or whatever be needed to prevent parallax to sell the design?

    When Parallax were doing the layout by themselves, they could modify the design at will. But now that they get the design from Treehouse Designs and I think they don't have a second chance without paying big $$$.

    Have we been able to document, completely understand, and verify the P1V code? How is it possible that we can help Parallax to test the P2 when we have not done that yet for the P1v? Does Parallax or the design house need any help from us? I think not.

    But said that those seventy-five $500 fpga boards have not been made to be wasted, so someday maybe we will have the fpga image.
  • evanhevanh Posts: 16,041
    edited 2015-03-12 13:52
    The prior art is right here in public view. There's something broken with the patent office if it can't deal with that. That said, I'm not advocating for having the P2-HOT source published because that'd divert Chip's attention.

    As for the FPGA boards, I think most people here will be testing with their applications. Documentation and understanding and bugs found will all be a side effect of questions being raised when trying to make it work.
  • Kerry SKerry S Posts: 163
    edited 2015-03-13 09:08
    evanh wrote: »
    The prior art is right here in public view.

    Prior art no longer matters, the recent changes to patent law 'reform' moved from the "First to Invent" where prior art was considered to "First to File". Thus making it easier for Apple, and the other big corporations, to see something they like and patent it out from under smaller innovators.
  • TorTor Posts: 2,010
    edited 2015-03-15 04:42
    Kerry S wrote: »
    Prior art no longer matters, the recent changes to patent law 'reform' moved from the "First to Invent" where prior art was considered to "First to File". Thus making it easier for Apple, and the other big corporations, to see something they like and patent it out from under smaller innovators.
    No, that's backwards. Nothing changed with respect to prior art (as in previuosly published). The small guy is *much* better off now, because if you a) file a patent), and b) nothing has been published before (no prior art), then there can be no c) BigCorp moves in after you and say "nono, we got it all along in the lab". And d) your filed-first patent gets replaced by theirs. The change prevents c) and d). But nothing changed w.r.t. "you can't patent something already published" (except of course the inability of patent offices to actually look for that).
    In any case, this is how patent law has worked in other countries for a very long time already. Except for one difference - read about it on Wikipedia.
  • Kerry SKerry S Posts: 163
    edited 2015-03-15 12:59
    You assume that the small guy can afford to patent every aspect of every innovation that they come up with... or that the patent $$ will pay off in real protection to justify the high costs.

    That is exactly the problem with moving to First to File. The US PTO does not look at prior art hardly at all, if at all when dealing with an Apple/MS type case. So if they see something they like, that has NOT been patented yet, they just file on it. They have the budgets and legal people on staff to do it.

    You have to realize that in this country (USA) the only marginal benefit you get as a small company for patenting an idea is limited protection from a big corporation from patenting and suing you over your own invention. The Chinese will just knock you off regardless and if you spend the $$$ to try to block them, and get anyone to issue an injunction to stop them which is almost impossible, they simply rebrand it through another shell company and keep on selling. A big company can, and will, bankrupt any small company who tries to go after them in court especially if they hold the cards (patent).

    I know that from first hand experience. Was Director of Engineering for a manufacturing company for 14 years and we had a number of patents, including some I invented. We had one really good one for a product that we showed Sears (big retailer here) and they wanted to use it in the Christmas specials. Only problem was that they wanted it for 25% cheaper than we priced it at. When our Owner pointed out that it was a unique item covered by our patent the Executive Buyer actually LAUGHED at him. Turns out they had already shopped the product samples we had given them to china and had 3 quotes direct from there. He then proceeded to tell us that "your patent means nothing to us as our legal department's budget is more than you make in a year. Give me the price I want or I buy elsewhere, sue me and I will drop you as a vendor and legal will keep the case in court until you are bankrupt."

    THAT is what our patent system has boiled down to here. You spend a bunch of money for one, and then the deck is stacked against you in trying to enforce it.

    First to File simply makes it even easier for an Apple/MS to ram a questionable patent through. Which is why they pushed so hard (and paid a lot of $$$ to politicians) to get it done. Prior art means nothing if Apple claims they invented it 'in parallel' in the same time frame as someone else THEY WIN right off the bat with First to File since at that point they have the patent and were clearly First to File.
  • potatoheadpotatohead Posts: 10,261
    edited 2015-03-15 14:20
    As a little guy in the middle of some filings, it does put some pressure on new product releases.

    On the flip side, in niches, patent pending has a little more teeth.

    The stuff I'm working on is novel mechanical. They do work considerably harder than the do the software stuff. We've seen claims from the 1900's cited frequently.

    First to file is a land grab in tech patents. For us, and mechanical, it means you can't even let a whiff leave the building. Prior art helped with this considerably. Since the land grab has happened to a large degree in the mechanical space, novel is hard to prove, and since so much is happening in tech, it also means getting less attention and or it has been harder to source really great people too.
  • evanhevanh Posts: 16,041
    edited 2015-03-15 14:21
    Kerry S wrote: »
    ... Prior art means nothing if Apple claims they invented it 'in parallel' in the same time frame as someone else THEY WIN right off the bat with First to File since at that point they have the patent and were clearly First to File.

    Prior art should still work if the evidence existed prior to the patent filing. Which obviously occurs when the source code is freely available.
  • rod1963rod1963 Posts: 752
    edited 2015-03-15 16:30
    How is it exactly obvious when source code is available, please explain?

    Have you tried using that as a defense in court?
  • GordonMcCombGordonMcComb Posts: 3,366
    edited 2015-03-15 17:58
    Some folks seem to be confusing prior art and prior disclosure. The latter is a limited protection provided only by the US; if you plan to file, and your market is beyond the US, you should not disclose.

    Prior art in any published form, or disclosed in previously granted patent, is still a principal part of patent discovery. FITF doesn't change that. Applicants are still expected to be thorough and disclose their discovery to the fullest extent, though sometimes a patent is granted that should not have been given the existence of prior art. But that was also a problem with first to invent. The patent office didn't, and still doesn't, keep tabs on forums like this one.

    One major change in favor of the independent inventor is the fee structure. It cost very little for a small entity to initially file. The playing field is much more level now.

    But all this begs the question: what about the P2 is patentable, and would they care? I see Parallax as a company that places far more value in customer support and education of its products. It's not just a simple question of someone else seeing what the P2 can do, and realizing it's not yet filed, send in a claim. It (still) doesn't work that way.
  • evanhevanh Posts: 16,041
    edited 2015-03-15 19:10
    rod1963 wrote: »
    How is it exactly obvious when source code is available, please explain?

    For providing a dependable date-stamp of the original webpage, http://archive.org/web/web.php is a good start. How much of the original content gets mirrored might depend on how the content is managed though. I'm no web expert.

    Here's an example - http://web.archive.org/web/20130713003048/http://forums.parallax.com/showthread.php/125543-Propeller-II-update-BLOG
    From the link you can see the snapshot was taken July 2013 and that dates are present on the topic posts. That's pretty good data to work with if one was trying to piece together believable evidence.
  • TorTor Posts: 2,010
    edited 2015-03-16 00:34
    Kerry S wrote: »
    First to File simply makes it even easier for an Apple/MS to ram a questionable patent through. Which is why they pushed so hard (and paid a lot of $$$ to politicians) to get it done. Prior art means nothing if Apple claims they invented it 'in parallel' in the same time frame as someone else THEY WIN right off the bat with First to File since at that point they have the patent and were clearly First to File.
    Kerry, I have no issues with what you explained about your experiences with bigcorp. It's not a good state of affairs. What I have problems with is why you think it's worse now. Because what you describe in what I quote above is *easier* for Apple (or some other bigcorp) with First to Invent, because they can always claim that they did this 'in parallel' (or 'before') even if you, in fact, filed first. Now you can file first, and then you have the patent. What happens after that seems to be independent of FTF, FTI, FITF: The guys with the money believe they have the right (as you experienced). That is a different, and unfortunate, story.
  • average joeaverage joe Posts: 795
    edited 2015-03-17 09:47
    Parallax runs on Valve Time... I thought you guys knew this by now ;)

    https://developer.valvesoftware.com/wiki/Valve_Time
  • mindrobotsmindrobots Posts: 6,506
    edited 2015-03-17 10:13
    Parallax runs on Valve Time... I thought you guys knew this by now ;)

    https://developer.valvesoftware.com/wiki/Valve_Time

    Excellent!

    "Coincident with the Rapture" as a target date almost got Pepsi on the keyboard!

    I'll have to work that into one of my project schedules and see if anyone notices.
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