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Verilog modifications (minimalist P1V) — Parallax Forums

Verilog modifications (minimalist P1V)

RamonRamon Posts: 484
edited 2015-03-04 03:32 in Propeller 1
Is there a thread to collect small recipes on how to remove P1 Verilog code? reduce the number the of cogs? and reduce RAM/ROM?

For example, how to properly remove video (cog_vid.v)? I am thinking of doing this:

- remove wires "vidack" and "vid_pin_out"
- remove 32-bit regs "s" and "d"?
- remove instantiation of video module (cog_vid_ ).
- Modify waitx (remove the line that contains "vidack")
...

Is it possible to reasign the WAITVID opcode to other custom function? or this instruction is used by bootloader?

The purpose is to experiment, have room for more opcodes or logic elements, and impement weird instructions (like BCD, CRC, etc ...)

Comments

  • SeairthSeairth Posts: 2,474
    edited 2015-03-02 11:08
    I don't think there's been a central location for that information. You can find some of it by digging through the forum, and I believe a few of those variants have been checked into github (as forks from https://github.com/ZiCog/P8X32A_Emulation). I like the idea of having a central place for these kinds of general tweaks. Not sure where it should be located or how it should be organized, though.
  • jmgjmg Posts: 15,173
    edited 2015-03-02 13:57
    Ramon wrote: »
    Is there a thread to collect small recipes on how to remove P1 Verilog code? reduce the number the of cogs? and reduce RAM/ROM?

    Not a specific thread, but the best code-base-fork would likely be here :
    http://forums.parallax.com/showthread.php/160016-First-attempt-at-building-a-P1V-image-for-the-BeMicro-Max10
    There, ozpropdev has builds with fewer/no Video and some with additional Counters, and he has also minimised the ROM footprint to just the boot elements.
  • ozpropdevozpropdev Posts: 2,792
    edited 2015-03-02 17:26
    Hi All
    I have a tool that builds custom P1V's in various combinations with user input on specs. i.e. number of cogs,counters,ram io pins clock speed etc.
    It also builds custom rom images for modified booters, interpreters as well.
    The tool produces all the Verilog files with comments on the changes made.
    I hope to post the tool and documentation in the next couple of days. :)
    Cheers
    Brian
  • mindrobotsmindrobots Posts: 6,506
    edited 2015-03-02 20:18
    Can you feed it the specs for the P2? You would be a hero!!

    :0)
  • TubularTubular Posts: 4,702
    edited 2015-03-02 21:35
    Just have a permanently greyed out option

    [ ] Generate P2 verilog
  • porcupineporcupine Posts: 80
    edited 2015-03-03 12:22
    Is your script capable of creating Verilog with HUB/COG RAM larger than 32k/2k? I wasn't sure with the current state of things if those limits had been broken yet?
  • jmgjmg Posts: 15,173
    edited 2015-03-03 12:38
    porcupine wrote: »
    Is your script capable of creating Verilog with HUB/COG RAM larger than 32k/2k? I wasn't sure with the current state of things if those limits had been broken yet?
    HUB ram over 32k would be relatively easy, ( it has already been sized-down), but COG ram over 2k would need opcode changes.
  • ozpropdevozpropdev Posts: 2,792
    edited 2015-03-04 03:32
    The tool does support larger hub ram (32,48,56 and 60k) are supported.
    Changing cog ram is a lot more complex and "breaks" compatibility with Spin/PASM.
    I'm trying to complete the documentation now, but work keeps getting in the way. :(
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