Counter Register Name Meanings

RobertDyer

As I get deeper into the Propeller, and I'm starting to use the Counters, at times I struggle with the features of some of the Counter Modes. One of the things that's hampering me is that I don't understand the meanings of the names Phase Register (PHSx) and Frequency Register (FRQx). I haven't seen an explanation in any of the literature that "clicks" for me. Would someone please explain why why the Accumulator is called the Phase Register, and what I would call the "Delta" Register is called the Frequency Register?

I think once I have an intuitive sense of those meanings I'll better understand how the Propeller designers intended the various Counter Modes to be used, and I'll be through this current mental block. (61 YO neurons just don't seem to fire as quickly as they used to!)

Thanks!

evanh

Your understanding of function is correct. Chip probably didn't want to name the registers as counter or accumulator because those are so common, dunno. I suspect the naming is in relation to PLL modes.

Tubular

The Phase register is indeed quite accurate. Think of 0 as being 0 degrees, $7fff ffff as being very nearly 180 degrees, then as you count further you end up at $ffffffff just before rolling back through zero. Picking off the MSB (bit 31) is an easy way to get a square wave out

Every clock tick you add the contents of FRQ (if your selected logic conditions say so) to PHS. So you can roll around fast (by adding a big FRQ value each clock tick, or really slowly, by just adding FRQ=1 each clock, or anywhere in between for quite fine-grained control of frequency. If FRQ=1 it'll take something like 53 seconds to roll PHS all the way through its 32 bit count cycle.

This understanding is also related to "DDS" (sine wave) techniques, instead of just pulling off the top bit 31, you simply take off the top 12 bits to feed to a DAC (edit: via a sine lookup table as Mark_T correctly points out)

Mark_T

This is how you do Direct Digital Synthesis (DDS). Its simply one of many discrete difference techniques
out there to do higher order operations using integer CPUs:

phase += frequency
output = sinetable [phase]

Here the counter hardware can do the first line automatically but not the table lookup - but you can get
a square wave.

The names aren't so meaningful if you aren't generating waveforms or driving waitvid of course.

T Chap

Robert, have you looked over the counter app note?