BOM ideas for a combined P1 and P1V Development Module
jmg
Posts: 15,173
Purpose :
A P1 and Max10 FPGA Board, where a moderate sized Max10 can augment the P1, with better peripherals.
This could give a good test vehicle for P2 peripheral field testing, as well as seed commercial projects that could switch to P2 when released.
Targets: Needs to be as small, and cheap as possible.
Areas of Variation: The JTAG loader is the largest 'deadweight' cost on many modules.
eg The $30 BeMicro MAX10 has a [FT240 + MAX V 5M80ZE64 CPLD] on board.
The $89 Macnica boards use a largish, not cheap 32bit MCU (EFM32GG395) for Loader.
Standard Prop PCBs use a Low cost USB-Serial Bridge, Initial speed need for P1 load is 115200 Baud.
Higher speeds are really needed for JTAG loading, but the P1 can manage that ?
Targets of 3-6 Mbaud * would allow better USB-UARTs to be supported longer term.
There are other JTAG designs out there, one is at http://www.ixo.de/ looks promising.
This uses FT245 + Modest CPLD, which opens up a solution of
a) the FT245 block is emulated with a FIFO Serial, using 1-2 COGS in the P1
(because speed matters, I'd guess 2 COGS, one for Rx and, one for Tx FIFO manage)
b) the CPLD (VHDL code below) is emulated in a 3rd COG that does FIFO-JTAG operate.
VHDL, ~ 120 Active Code lines, seems to be two state engines, that would code to PASM - because the link is a FIFO, exact speed matching is not important - just as fast as practical.
The 4 JTAG MAX 10 pins, would connect to 4 P1 pins.
That JTAG path should support other device pgm, with a pin header.
To Program the MAX 10 FPGA, the P1 has 3 COGS preloaded with the 'blaster' bridge
After that, those COGs can be reloaded with user SW.
Is anyone able to offer Peak Baud rate numbers for 1 & 2 COGS as UART-FIFO block ?
*Addit:
Links for Serial code and comments on speed
3M Rx
http://forums.parallax.com/showthread.php/160116-Trouble-with-serial-receive-code?p=1316419&viewfull=1#post1316419
5M half duplex
http://forums.parallax.com/showthread.php/160113-Extra-bit-time-in-FullDuplexSerial?p=1316422&viewfull=1#post1316422
Addit2: Code for PC end of USB_Blaster, includes command table for Bitbang/Bytes & simplex/duplex control bits
http://openocd.sourceforge.net/doc/doxygen/html/usb__blaster_8c_source.html
Comment on ID checking
http://www.openjtag.org/index.php?option=com_agora&task=topic&id=6&Itemid=57
A P1 and Max10 FPGA Board, where a moderate sized Max10 can augment the P1, with better peripherals.
This could give a good test vehicle for P2 peripheral field testing, as well as seed commercial projects that could switch to P2 when released.
Targets: Needs to be as small, and cheap as possible.
Areas of Variation: The JTAG loader is the largest 'deadweight' cost on many modules.
eg The $30 BeMicro MAX10 has a [FT240 + MAX V 5M80ZE64 CPLD] on board.
The $89 Macnica boards use a largish, not cheap 32bit MCU (EFM32GG395) for Loader.
Standard Prop PCBs use a Low cost USB-Serial Bridge, Initial speed need for P1 load is 115200 Baud.
Higher speeds are really needed for JTAG loading, but the P1 can manage that ?
Targets of 3-6 Mbaud * would allow better USB-UARTs to be supported longer term.
There are other JTAG designs out there, one is at http://www.ixo.de/ looks promising.
This uses FT245 + Modest CPLD, which opens up a solution of
a) the FT245 block is emulated with a FIFO Serial, using 1-2 COGS in the P1
(because speed matters, I'd guess 2 COGS, one for Rx and, one for Tx FIFO manage)
b) the CPLD (VHDL code below) is emulated in a 3rd COG that does FIFO-JTAG operate.
VHDL, ~ 120 Active Code lines, seems to be two state engines, that would code to PASM - because the link is a FIFO, exact speed matching is not important - just as fast as practical.
The 4 JTAG MAX 10 pins, would connect to 4 P1 pins.
That JTAG path should support other device pgm, with a pin header.
To Program the MAX 10 FPGA, the P1 has 3 COGS preloaded with the 'blaster' bridge
After that, those COGs can be reloaded with user SW.
Is anyone able to offer Peak Baud rate numbers for 1 & 2 COGS as UART-FIFO block ?
------------------------------------------------------------------------------- -- Serial/Parallel converter, interfacing JTAG chain with FTDI FT245BM ------------------------------------------------------------------------------- -- Copyright (C) 2005-2007 Kolja Waschk, ixo.de ------------------------------------------------------------------------------- -- This code is part of usbjtag. usbjtag is free software; you can redistribute -- it and/or modify it under the terms of the GNU General Public License as -- published by the Free Software Foundation; either version 2 of the License, -- or (at your option) any later version. usbjtag is distributed in the hope -- that it will be useful, but WITHOUT ANY WARRANTY; without even the implied -- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. You should have received a -- copy of the GNU General Public License along with this program in the file -- COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin -- St, Fifth Floor, Boston, MA 02110-1301 USA ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY jtag_logic IS PORT ( CLK : IN STD_LOGIC; -- external 24/25 MHz oscillator nRXF : IN STD_LOGIC; -- FT245BM nRXF nTXE : IN STD_LOGIC; -- FT245BM nTXE B_TDO : IN STD_LOGIC; -- JTAG input: TDO, AS/PS input: CONF_DONE B_ASDO : IN STD_LOGIC; -- AS input: DATAOUT, PS input: nSTATUS B_TCK : out STD_LOGIC; -- JTAG output: TCK to chain, AS/PS DCLK B_TMS : out STD_LOGIC; -- JTAG output: TMS to chain, AS/PS nCONFIG B_NCE : out STD_LOGIC; -- AS output: nCE B_NCS : out STD_LOGIC; -- AS output: nCS B_TDI : out STD_LOGIC; -- JTAG output: TDI to chain, AS: ASDI, PS: DATA0 B_OE : out STD_LOGIC; -- LED output/output driver enable nRD : OUT STD_LOGIC; -- FT245BM nRD WR : OUT STD_LOGIC; -- FT245BM WR D : INOUT STD_LOGIC_VECTOR(7 downto 0); -- FT245BM D[7..0] led : out std_logic := '1' ); END jtag_logic; ARCHITECTURE spec OF jtag_logic IS -- There are exactly 16 states. If this is encoded using 4 bits, there will -- be no unknown/undefined state. The host will send us 64 times "0" to move -- the state machine to a known state. We don't need a power-on reset. TYPE states IS ( wait_for_nRXF_low, set_nRD_low, keep_nRD_low, latch_data_from_host, set_nRD_high, bits_set_pins_from_data, bytes_set_bitcount, bytes_get_tdo_set_tdi, bytes_clock_high_and_shift, bytes_keep_clock_high, bytes_clock_finish, wait_for_nTXE_low, set_WR_high, output_enable, set_WR_low, output_disable ); ATTRIBUTE ENUM_ENCODING: STRING; ATTRIBUTE ENUM_ENCODING OF states: TYPE IS "0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111"; SIGNAL carry: STD_LOGIC; SIGNAL do_output: STD_LOGIC; SIGNAL ioshifter: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL bitcount: STD_LOGIC_VECTOR(8 DOWNTO 0); SIGNAL state, next_state: states; SIGNAL ncs: std_logic; BEGIN sm: PROCESS(nRXF, nTXE, state, bitcount, ioshifter, do_output) BEGIN CASE state IS -- ============================ INPUT WHEN wait_for_nRXF_low => IF nRXF='0' THEN next_state <= set_nRD_low; ELSE next_state <= wait_for_nRXF_low; END IF; WHEN set_nRD_low => next_state <= keep_nRD_low; WHEN keep_nRD_low => next_state <= latch_data_from_host; WHEN latch_data_from_host => next_state <= set_nRD_high; WHEN set_nRD_high => IF NOT (bitcount(8 DOWNTO 3) = "000000") THEN next_state <= bytes_get_tdo_set_tdi; ELSIF ioshifter(7) = '1' THEN next_state <= bytes_set_bitcount; ELSE next_state <= bits_set_pins_from_data; END IF; WHEN bytes_set_bitcount => next_state <= wait_for_nRXF_low; -- ============================ BIT BANGING WHEN bits_set_pins_from_data => IF ioshifter(6) = '0' THEN next_state <= wait_for_nRXF_low; -- read next byte from host ELSE next_state <= wait_for_nTXE_low; -- output byte to host END IF; -- ============================ BYTE OUTPUT (SHIFT OUT 8 BITS) WHEN bytes_get_tdo_set_tdi => next_state <= bytes_clock_high_and_shift; WHEN bytes_clock_high_and_shift => next_state <= bytes_keep_clock_high; WHEN bytes_keep_clock_high => next_state <= bytes_clock_finish; WHEN bytes_clock_finish => IF NOT (bitcount(2 DOWNTO 0) = "111") THEN next_state <= bytes_get_tdo_set_tdi; -- clock next bit ELSIF do_output = '1' THEN next_state <= wait_for_nTXE_low; -- output byte to host ELSE next_state <= wait_for_nRXF_low; -- read next byte from host END IF; -- ============================ OUTPUT BYTE TO HOST WHEN wait_for_nTXE_low => IF nTXE = '0' THEN next_state <= set_WR_high; ELSE next_state <= wait_for_nTXE_low; END IF; WHEN set_WR_high => next_state <= output_enable; WHEN output_enable => next_state <= set_WR_low; WHEN set_WR_low => next_state <= output_disable; WHEN output_disable => next_state <= wait_for_nRXF_low; -- read next byte from host WHEN OTHERS => next_state <= wait_for_nRXF_low; END CASE; END PROCESS sm; out_sm: PROCESS(CLK) BEGIN IF CLK = '1' AND CLK'event THEN IF state = set_nRD_low OR state = keep_nRD_low OR state = latch_data_from_host THEN nRD <= '0'; ELSE nRD <= '1'; END IF; IF state = latch_data_from_host THEN led <= '1'; ioshifter(7 DOWNTO 0) <= D; END IF; IF state = set_WR_high OR state = output_enable THEN WR <= '1'; ELSE WR <= '0'; END IF; IF state = output_enable OR state = set_WR_low THEN led <= '0'; D <= ioshifter(7 DOWNTO 0); ELSE D <= "ZZZZZZZZ"; END IF; IF state = bits_set_pins_from_data THEN B_TCK <= ioshifter(0); B_TMS <= ioshifter(1); B_NCE <= ioshifter(2); B_NCS <= ioshifter(3); B_TDI <= ioshifter(4); B_OE <= ioshifter(5); ncs <= ioshifter(3); ioshifter <= "000000" & B_ASDO & B_TDO; END IF; IF state = bytes_set_bitcount THEN bitcount <= ioshifter(5 DOWNTO 0) & "111"; do_output <= ioshifter(6); END IF; IF state = bytes_get_tdo_set_tdi THEN IF ncs = '1' THEN carry <= B_TDO; -- JTAG mode (nCS=1) ELSE carry <= B_ASDO; -- Active Serial mode (nCS=0) END IF; B_TDI <= ioshifter(0); bitcount <= bitcount - 1; END IF; IF state = bytes_clock_high_and_shift OR state = bytes_keep_clock_high THEN B_TCK <= '1'; END IF; IF state = bytes_clock_high_and_shift THEN ioshifter <= carry & ioshifter(7 DOWNTO 1); END IF; IF state = bytes_clock_finish THEN B_TCK <= '0'; END IF; state <= next_state; END IF; END PROCESS out_sm; END spec;
*Addit:
Links for Serial code and comments on speed
3M Rx
http://forums.parallax.com/showthread.php/160116-Trouble-with-serial-receive-code?p=1316419&viewfull=1#post1316419
5M half duplex
http://forums.parallax.com/showthread.php/160113-Extra-bit-time-in-FullDuplexSerial?p=1316422&viewfull=1#post1316422
Addit2: Code for PC end of USB_Blaster, includes command table for Bitbang/Bytes & simplex/duplex control bits
http://openocd.sourceforge.net/doc/doxygen/html/usb__blaster_8c_source.html
Comment on ID checking
http://www.openjtag.org/index.php?option=com_agora&task=topic&id=6&Itemid=57
Comments
I don't know where Joe Grand's Jtagulator might fit in this
Personally I'm happy with the 10 pin jtag header and the terasic jtag progammer (~$50). I am thinking of paralleling up at least some pins to be analog inputs to the Max10 when jtag is not in place, I guess leaving off the clock pin so there isn't the chance of accidently programming something
Good to explore other options though
I had forgotten/missed that. That means they already have this pathway underway, which should make the SW common.
Their Cyclone V FPGA board will also be expensive, and not a broad use item.
This module drops in below the Cyclone V board, & above Quickstart, and will allow some P2-like developments.
A RaspPi expansion header would be logical.
Personally I've been burned on 3rd party FPGA boards - like that junky BeScope. The people who put that together didn't give a rats behind about quality or polish that's for sure. I won't touch anything except Terasics now.
Are you talking about the Cyclone V board, (which will be hundreds of Dollars) or a [P1 + Max 10], which could be in the region of $40 or even RaspPi$ ?
Parallax plan to do this pathway on their P2 Board, with the much larger FPGA.
From what I have gleaned, clone of USB-Blaster link, HW wise, is reasonable, only fish-hook is some mention the Quartus expects a single USB ID - that's easy enough to set, but then that may make a Serial channel harder.
I believe the Parallax FPGA board is close to release, so more details of this sort of issue will be exposed then.
Parallax's Board is in an entirely different level than your ~$30 ? $40 ? board... One could have a header for jtag and maybe two boards one with and one without jtag. One may want to use the board in some project and he extra baggage would increase cost, consumption, (something else).
Sure, of course, it is easy enough to subset a design.
I would encourage JTAG pins anyway, that can work in either direction. PCB PADS are a almost zero cost option
However, I would expect Parallax would first release the 'Easy to Use' model as that fits their customer base better.
- Just like there could be a choice of MAX10, once all the variants are out there. There are compatible footprints, so that's only an assembly option & toolchain setting.
If the P1 does JTAG, the only question is what chip to use for USB, and I see the choice expands
Today's news has "SiLabs: Starting prices from $0.43 (10k) for EFM8UB" - that part can manage RST reducing BOM further, and simplifying setups.
Nice find. These also have 12 bit ADCs and some kind of crossbar switch flexibility, and go down to 3x3mm. I have the local rep chasing one of the 5 dev kits shown in stock
EFM8 were showing up earlier on DigiKey from 31c/1k, - way below any ADC out there, let alone 12b ones.
Digikey seems to be re-entering them, as nothing finds right now.
Update: Back & visible again, (mostly) - seems to drop from a package filter ?
I suspect the incomplete fields affect this - still a WIP.
Just be a little cautious of the 'crossbar', is it not quite a classic any-to-any, but more a selection tree.
It does avoid the dual-use conundrum, but a late-change PCB pin-swap it is not.
I think we can get slave IO to run at 3MHz in these parts.
http://www.digikey.com/product-detail/en/SLSTK2001A/336-3157-ND