Heresy!!!!

rjo__

When I look at fmax ... it always reports the lowest figures connected to the counters....
So, not that I would use it for everything... but I think it would be useful to neuter my 4cogP1V on occasions....

Naturally, since I am sometimes in an addled state, it is probably is best to ask for advice.

How do I get rid of the counters and still have a functional P1V?

If you have done it already... please share or offer general pointers to the interesting bits.

And of course... does it really make sense to do this?

Thanks,

Rich

ozpropdev

Rich
You should be able to comment out the counter stuff in cog.v

// ctra/ctrb

wire [32:0] phsa;
wire [31:0] ctra_pin_out;
wire plla;

cog_ctr cog_ctra  (	.clk_cog	(clk_cog),
					.clk_pll	(clk_pll),
					.ena		(ena),
					.setctr		(setctra),
					.setfrq		(setfrqa),
					.setphs		(setphsa),
					.data		(alu_r),
					.pin_in		(pin_in),
					.phs		(phsa),
					.pin_out	(ctra_pin_out),
					.pll		(plla) );

wire [32:0] phsb;
wire [31:0] ctrb_pin_out;
wire pllb;

cog_ctr cog_ctrb  (	.clk_cog	(clk_cog),
					.clk_pll	(clk_pll),
					.ena		(ena),
					.setctr		(setctrb),
					.setfrq		(setfrqb),
					.setphs		(setphsb),
					.data		(alu_r),
					.pin_in		(pin_in),
					.phs		(phsb),
					.pin_out	(ctrb_pin_out),
					.pll		(pllb) );

assign pll_out		= plla;

and disconnect the counters from the pins

assign pin_out		= (outa | ctra_pin_out | ctrb_pin_out | vid_pin_out) & dira;
change to
assign pin_out		= (outa |  vid_pin_out) & dira;

A starting point...
Cheers
Brian

ozpropdev

Also in cog.v remove these two lines from the /source section

					: i[sh:sl] == 9'h1FC	? phsa[31:0]
					: i[sh:sl] == 9'h1FD	? phsb[31:0]

rjo__

exactly what i needed...

Of course, if it works the way I expect... then I'm going to need a multi-P1V.... which will bring me back to you with more questions.

cheers

By the way... I think your work on the BeMicro Max10 is just what the doctor ordered. Hope Ken is watching.

jmg

rjo__ wrote: »

When I look at fmax ... it always reports the lowest figures connected to the counters....

How much lower ?
I'm also not certain the P1V Verilog has full timing validity, didn't Chip mention something about multiple-clock paths not being tool identified ?

Even if you remove the Counter cells, presumably you still need CNT which will have a similar speed ?

rjo__

it's about 50% of the next worst case.

"Even if you remove the Counter cells, presumably you still need CNT which will have a similar speed ?"

ok... I don't know... any way to make that particular path more friendly?

Seairth

jmg wrote: »

I'm also not certain the P1V Verilog has full timing validity, didn't Chip mention something about multiple-clock paths not being tool identified ?

To get more accurate timing estimates, try using the SDC files for the DE0-Nano or DE2-115 that can be found here:

https://github.com/jacgoudsmit/P1V/tree/master/HDL

I haven't figured out how to properly reference Cyclone V PLLs yet, so there isn't a SDC for the MeMicroCV. And I haven't even started looking at the MAX10, so you are on your own there.

Also, note that most of the SDC contents can be removed if you also remove the counters.

rjo__

Seairth,

You always seem to be around when I am most perplexed and I thank you for your continued help.

I have to put my FPGA work on hold for the next three weeks..... taking the rugrat out to see grandma in Vegas. I am going to try to keep up with my thread in the General discussion... It's going to be a very long thread. There's no hurry, but it is something I really want to do and something I can do while sitting at the pool.

On the positive side, we are going to be exposing ourselves to the residuals of the recent measles epidemic at Disney, and if I can sneek away, I am going to see if I can figure out who is who and what is what.

I think we are seeing a new paradigm developing here. I would call it the Parallax Paradigm. I think the Magic Kingdom should be interested.

Everyone I knew a long time ago is gone... so no-one's feeling should be hurt when I point them to the fact that they made a huge technical analysis error on material that I forwarded them and they wouldn't want to repeat that again in the current environment... it is a long shot, but there is plenty of meat on the bone ... as they say... and the moment couldn't be more precient for them... and everyone else for that matter... time to think out of the box on security issues... and update those controllers while they are at it:)

Cheers!!!